threephaseengine12.asm

microchip公司的PICPIC18F系列芯片固件

ENERGY_VAR_7_0		EQU	0x200		; Total raw reactive energy accumulated so far
ENERGY_VAR_15_8		EQU	0x201
ENERGY_VAR_23_16	EQU	0x202
ENERGY_VAR_31_24	EQU	0x203
ENERGY_VAR_39_32	EQU	0x204
ENERGY_VAR_47_40	EQU	0x205
ENERGY_VAR_55_48	EQU	0x206
ENERGY_VAR_63_56	EQU	0x207

ENERGY_VAR_Z_7_0	EQU	0x208		; Total raw reactive energy accumulated since the
ENERGY_VAR_Z_15_8	EQU	0x209		;  last read of this register
ENERGY_VAR_Z_23_16	EQU	0x20A
ENERGY_VAR_Z_31_24	EQU	0x20B
ENERGY_VAR_Z_39_32	EQU	0x20C
ENERGY_VAR_Z_47_40	EQU	0x20D
ENERGY_VAR_Z_55_48	EQU	0x20E
ENERGY_VAR_Z_63_56	EQU	0x20F

ENERGY_VAR_L_RAW_7_0	EQU	0x210		; Total raw reactive energy accumulated over
ENERGY_VAR_L_RAW_15_8	EQU	0x211		;  the last LINE_CYC line cycles
ENERGY_VAR_L_RAW_23_16	EQU	0x212
ENERGY_VAR_L_RAW_31_24	EQU	0x213
ENERGY_VAR_L_RAW_39_32	EQU	0x214
ENERGY_VAR_L_RAW_47_40	EQU	0x215

ENERGY_VAR_L_7_0	EQU	0x216		; Total reactive energy, in X KVARHr/LSB, over
ENERGY_VAR_L_15_8	EQU	0x217		;  the last LINE_CYC line cycles
ENERGY_VAR_L_23_16	EQU	0x218
ENERGY_VAR_L_31_24	EQU	0x219

DUMMY_VAL_I_7_0		EQU	0x23C		; Dummy value for current, used for simulated cal
DUMMY_VAL_I_15_8	EQU	0x23D
DUMMY_VAL_V_7_0		EQU	0x23E		; Dummy value for voltage, used for simulated cal
DUMMY_VAL_V_15_8	EQU	0x23F

USER_BANK2_END		EQU	0x23F		; End user bank 2

; User accessible calibration registers

CAL_BANK		EQU	0x240		; Calibration bank, must follow user bank 2

PHA_DELAY		EQU	0x240		; Phase delay corrections, +/-2.8125 degrees
PHB_DELAY		EQU	0x241
PHC_DELAY		EQU	0x242

PHA_I_RMS_OFF_7_0	EQU	0x244		; Phase A RMS current offset squared
PHA_I_RMS_OFF_15_8	EQU	0x245

PHA_V_RMS_OFF_7_0	EQU	0x246		; Phase A RMS voltage offset squared
PHA_V_RMS_OFF_15_8	EQU	0x247

PHB_I_RMS_OFF_7_0	EQU	0x248		; Phase B RMS current offset squared
PHB_I_RMS_OFF_15_8	EQU	0x249

PHB_V_RMS_OFF_7_0	EQU	0x24A		; Phase B RMS voltage offset squared
PHB_V_RMS_OFF_15_8	EQU	0x24B

PHC_I_RMS_OFF_7_0	EQU	0x24C		; Phase C RMS current offset squared
PHC_I_RMS_OFF_15_8	EQU	0x24D

PHC_V_RMS_OFF_7_0	EQU	0x24E		; Phase C RMS voltage offset squared
PHC_V_RMS_OFF_15_8	EQU	0x24F

PHA_I_RMS_GAIN_7_0	EQU	0x250		; Phase A RMS current gain correction
PHA_I_RMS_GAIN_15_8	EQU	0x251

PHA_V_RMS_GAIN_7_0	EQU	0x252		; Phase A RMS voltage gain correction
PHA_V_RMS_GAIN_15_8	EQU	0x253

PHB_I_RMS_GAIN_7_0	EQU	0x254		; Phase B RMS current gain correction
PHB_I_RMS_GAIN_15_8	EQU	0x255

PHB_V_RMS_GAIN_7_0	EQU	0x256		; Phase B RMS voltage gain correction
PHB_V_RMS_GAIN_15_8	EQU	0x257

PHC_I_RMS_GAIN_7_0	EQU	0x258		; Phase C RMS current gain correction
PHC_I_RMS_GAIN_15_8	EQU	0x259

PHC_V_RMS_GAIN_7_0	EQU	0x25A		; Phase C RMS voltage gain correction
PHC_V_RMS_GAIN_15_8	EQU	0x25B

NEUT_I_RMS_GAIN_7_0	EQU	0x25C		; Neutral RMS current gain correction
NEUT_I_RMS_GAIN_15_8	EQU	0x25D

NEUT_V_RMS_GAIN_7_0	EQU	0x25E		; Neutral RMS voltage gain correction
NEUT_V_RMS_GAIN_15_8	EQU	0x25F

PHA_I_RMS_GLSB_7_0	EQU	0x260		; Phase A current gain to produce X A/LSB
PHA_I_RMS_GLSB_15_8	EQU	0x261

PHA_V_RMS_GLSB_7_0	EQU	0x262		; Phase A voltage gain to produce X V/LSB
PHA_V_RMS_GLSB_15_8	EQU	0x263

PHB_I_RMS_GLSB_7_0	EQU	0x264		; Phase B current gain to produce X A/LSB
PHB_I_RMS_GLSB_15_8	EQU	0x265

PHB_V_RMS_GLSB_7_0	EQU	0x266		; Phase B voltage gain to produce X V/LSB
PHB_V_RMS_GLSB_15_8	EQU	0x267

PHC_I_RMS_GLSB_7_0	EQU	0x268		; Phase C current gain to produce X A/LSB
PHC_I_RMS_GLSB_15_8	EQU	0x269

PHC_V_RMS_GLSB_7_0	EQU	0x26A		; Phase C voltage gain to produce X V/LSB
PHC_V_RMS_GLSB_15_8	EQU	0x26B

NEUT_I_RMS_GLSB_7_0	EQU	0x26C		; Neutral current gain to produce X A/LSB
NEUT_I_RMS_GLSB_15_8	EQU	0x26D

NEUT_V_RMS_GLSB_7_0	EQU	0x26E		; Neutral voltage gain to produce X V/LSB
NEUT_V_RMS_GLSB_15_8	EQU	0x26F

PHA_W_OFF_7_0		EQU	0x270		; Phase A active power offset
PHA_W_OFF_15_8		EQU	0x271
PHA_W_OFF_23_16		EQU	0x272
PHA_W_OFF_31_24		EQU	0x273

PHB_W_OFF_7_0		EQU	0x274		; Phase B active power offset
PHB_W_OFF_15_8		EQU	0x275
PHB_W_OFF_23_16		EQU	0x276
PHB_W_OFF_31_24		EQU	0x277

PHC_W_OFF_7_0		EQU	0x278		; Phase C active power offset
PHC_W_OFF_15_8		EQU	0x279
PHC_W_OFF_23_16		EQU	0x27A
PHC_W_OFF_31_24		EQU	0x27B

PHA_W_GAIN_7_0		EQU	0x27C		; Phase A active power gain to equalize W/LSB
PHA_W_GAIN_15_8		EQU	0x27D

PHB_W_GAIN_7_0		EQU	0x27E		; Phase B active power gain to equalize W/LSB
PHB_W_GAIN_15_8		EQU	0x27F

PHC_W_GAIN_7_0		EQU	0x280		; Phase C active power gain to equalize W/LSB
PHC_W_GAIN_15_8		EQU	0x281

PHA_W_GLSB_7_0		EQU	0x282		; Phase A active power gain to produce X W/LSB
PHA_W_GLSB_15_8		EQU	0x283

PHB_W_GLSB_7_0		EQU	0x284		; Phase B active power gain to produce X W/LSB
PHB_W_GLSB_15_8		EQU	0x285

PHC_W_GLSB_7_0		EQU	0x286		; Phase C active power gain to produce X W/LSB
PHC_W_GLSB_15_8		EQU	0x287

PHA_VA_GAIN_7_0		EQU	0x288		; Phase A apparent power gain to equalize VA/LSB
PHA_VA_GAIN_15_8	EQU	0x289

PHB_VA_GAIN_7_0		EQU	0x28A		; Phase B apparent power gain to equalize VA/LSB
PHB_VA_GAIN_15_8	EQU	0x28B

PHC_VA_GAIN_7_0		EQU	0x28C		; Phase C apparent power gain to equalize VA/LSB
PHC_VA_GAIN_15_8	EQU	0x28D

PHA_VA_GLSB_7_0		EQU	0x28E		; Phase A apparent power gain to produce X VA/LSB
PHA_VA_GLSB_15_8	EQU	0x28F

PHB_VA_GLSB_7_0		EQU	0x290		; Phase B apparent power gain to produce X VA/LSB
PHB_VA_GLSB_15_8	EQU	0x291

PHC_VA_GLSB_7_0		EQU	0x292		; Phase C apparent power gain to produce X VA/LSB
PHC_VA_GLSB_15_8	EQU	0x293

PHA_VAR_GAIN_7_0	EQU	0x294		; Phase A reactive power gain to equalize VAR/LSB
PHA_VAR_GAIN_15_8	EQU	0x295

PHB_VAR_GAIN_7_0	EQU	0x296		; Phase B reactive power gain to equalize VAR/LSB
PHB_VAR_GAIN_15_8	EQU	0x297

PHC_VAR_GAIN_7_0	EQU	0x298		; Phase C reactive power gain to equalize VAR/LSB
PHC_VAR_GAIN_15_8	EQU	0x299

PHA_VAR_GLSB_7_0	EQU	0x29A		; Phase A reactive power gain to produce X VAR/LSB
PHA_VAR_GLSB_15_8	EQU	0x29B

PHB_VAR_GLSB_7_0	EQU	0x29C		; Phase B reactive power gain to produce X VAR/LSB
PHB_VAR_GLSB_15_8	EQU	0x29D

PHC_VAR_GLSB_7_0	EQU	0x29E		; Phase C reactive power gain to produce X VAR/LSB
PHC_VAR_GLSB_15_8	EQU	0x29F

ENERGY_W_GLSB_7_0	EQU	0x2A0		; Active energy gain to produce X WHr/LSB
ENERGY_W_GLSB_15_8	EQU	0x2A1

ENERGY_VA_GLSB_7_0	EQU	0x2A2		; Apparent energy gain to produce X VAHr/LSB
ENERGY_VA_GLSB_15_8	EQU	0x2A3

ENERGY_VAR_GLSB_7_0	EQU	0x2A4		; Reactive energy gain to produce X VARHr/LSB
ENERGY_VAR_GLSB_15_8	EQU	0x2A5

CREEP_THRESH_7_0	EQU	0x2A6		; Creep threshold for active energy. If the
CREEP_THRESH_15_8	EQU	0x2A7		;  energy over one line cycle is less than
CREEP_THRESH_23_16	EQU	0x2A8		;  this value and creep threshold is on, then
CREEP_THRESH_31_24	EQU	0x2A9		;  the energy will not be accumulated

CF_PULSE_WIDTH		EQU	0x2AA		; CF pulse width, t = value * ((1 / LineFreq) / 128)
CFDEN			EQU	0x2AC		; Coarse correction of active energy
CFNUM_7_0		EQU	0x2AE		; Fine gain correction of active energy for
CFNUM_15_8		EQU	0x2AF		;  CF pulse generation

MODE1_DEF_7_0		EQU	0x2B0		; Mode 1 default register, restored on
MODE1_DEF_15_8		EQU	0x2B1		;  power up

PHA_CAL_STATUS_7_0	EQU	0x2B2		; Phase A calibration status
PHA_CAL_STATUS_15_8	EQU	0x2B3

PHB_CAL_STATUS_7_0	EQU	0x2B4		; Phase B calibration status
PHB_CAL_STATUS_15_8	EQU	0x2B5

PHC_CAL_STATUS_7_0	EQU	0x2B6		; Phase C calibration status
PHC_CAL_STATUS_15_8	EQU	0x2B7

STAND_W_RAW_7_0		EQU	0x2B8		; Standard (cal reference) raw active power
STAND_W_RAW_15_8	EQU	0x2B9
STAND_W_RAW_23_16	EQU	0x2BA
STAND_W_RAW_31_24	EQU	0x2BB
STAND_W_RAW_39_32	EQU	0x2BC
STAND_W_RAW_47_40	EQU	0x2BD

I_CAL_MAX_7_0		EQU	0x2C0		; Maximum current specified during calibration
I_CAL_MAX_15_8		EQU	0x2C1

V_CAL_7_0		EQU	0x2C2		; Voltage specified during calibration
V_CAL_15_8		EQU	0x2C3

I_CAL_7_0		EQU	0x2C4		; Current specified during calibration
I_CAL_15_8		EQU	0x2C5

FREQ_CAL_7_0		EQU	0x2C6		; Frequency specified during calibration
FREQ_CAL_15_8		EQU	0x2C7

METER_CONST_7_0		EQU	0x2C8		; Meter constant specified during calibration
METER_CONST_15_8	EQU	0x2C9

METER_CONST_INV_7_0	EQU	0x2CA		; round((1/Meter Constant)*32767*256)
METER_CONST_INV_15_8	EQU	0x2CB

LINE_CYC_CAL_7_0	EQU	0x2CC		; Number of line cycles during calibration (2^LINE_CYC_CAL)
LINE_CYC_CAL_15_8	EQU	0x2CD

CAL_BANK_END		EQU	0x2FF		; End calibration bank


; Communications buffer must start on a 128 byte boundary!
; Can start on a 64 byte boundary, see INT2_Chk_RC and INT2_Chk_TX
CommsBuffer		EQU	0x300		; 64 byte input/output buffer for UART

ScratchPad		EQU	0x340		; Scratchpad area: 0x340 to 0x37F




	org	0x00
	nop
	bra	start





;***** High priority interrupt routine (timer 1 overflow to set CCP2 ****
;***** output low) ******************************************************
;************************************************************************
	org	0x08
	btfss	PIR1,TMR1IF,A			; Check for Timer 1 interrupt
	bra	INT2_Handler			; If not, handle other interrupts
#ifdef PLL_PRESENT
	movlw	b'00001000'			; Compare mode, initially low then high on match
	movwf	CCP2CON,A
	movlw	0x80
	movwf	TMR1H,A
#endif
	bcf	PIR1,TMR1IF,A
	retfie	FAST





;********* Low priority vector to low priority interrupt routine ********
;************************************************************************
	org	0x18
	bra	LowPriorityInterrupts






;************ Interrupt handler for high priority interrupts ************
;************************************************************************
INT2_Handler
	btfss	INTCON3,INT2IF,A		; Check for INT2 interrupt
	bra	INT2_Chk_RC			; Not IN2, check RC
	bcf	INTCON3,INT2IF,A		; Clear INT2 interrupt flag
	bcf	INTCON3,INT2IE,A		; Disable INT2 interrupt
	bcf	INTCON,TMR0IF,A			; Clear timer 0 interrupt flag
	movff	Timer0Set,TMR0L			; Set initial TMR0 value
	bsf	INTCON,TMR0IE,A			; Enable timer 0 interrupt
	retfie	FAST

INT2_Chk_RC
	btfss	PIR1,RCIF,A			; Check for RC interrupt
	bra	INT2_Chk_TX			; Not RC, check TX
	movf	RCREG,W,A			; Receive character
	btfsc	STATUS,Z,A			; If zero, ignore
	retfie	FAST
	btfsc	RCSTA,OERR,A			; If UART receive overrun, set error flag
	bsf	CommFlags,RCOverrun,A
	btfsc	CommFlags,RCDone,A		; If RCDone but not processed, set error flag
	bsf	CommFlags,BufOverrun,A
	btfsc	CommFlags,TXInProgress,A	; If TX in progress, set error flag
	bsf	CommFlags,BufOverrun,A
	btfsc	FSR2H,6,A			; If buffer ptr wrapped around, set error flag
;	btfss	FSR2H,6,A			; Use this if buffer starts at 0x40 or 0xC0
	bsf	CommFlags,BufOverflow,A
	movf	CommFlags,F,A			; If CommFlags not zero, do not store char
	btfsc	STATUS,Z,A
	movwf	POSTINC2,A
	sublw	TERM_CHAR			; Check for termination character
	btfsc	STATUS,Z,A
	bsf	CommFlags,RCDone,A		; If same, then RC is done
	btfss	RCSTA,OERR,A			; If no UART overrun, return
	retfie	FAST
	bcf	RCSTA,CREN,A			; UART overrun, clear it
	bsf	RCSTA,CREN,A
	retfie	FAST

INT2_Chk_TX
	movf	POSTINC2,W,A			; Fetch character
	movwf	TXREG,A				; Send to UART (and clear TXIF flag)
	sublw	TERM_CHAR			; Compare to termination character
	btfss	STATUS,Z,A			; If not term char, return
	retfie	FAST
	bcf	PIE1,TXIE,A			; If term char, clear TX int enable
	lfsr	2,CommsBuffer
	bcf	CommFlags,TXInProgress,A	;  and TX in progress flag
	retfie	FAST





;*********************** Low priority interrupts  ***********************
;************************************************************************
LowPriorityInterrupts

	movwf	LPI_SaveW,A			; Save critical registers
	movff	STATUS,LPI_SaveStatus
	movff	BSR,LPI_SaveBSR
	movff	PRODH,LPI_PRODH_Save
	movff	PRODL,LPI_PRODL_Save

	bcf	INTCON,TMR0IE,A			; Disable timer 0 interrupt
	bcf	INTCON,TMR0IF,A			; Clear timer 0 interrupt flag

#ifndef	ADC_MCP3909
	bsf	MPU_ADC_CSA,A			; Enable phase A ADC by setting its CS HIGH
	bcf	MPU_ADC_CSC,A			;  and phase C chip select LOW (phase B already LOW)
#endif
	; Get ADC results