threephaseengine12.asm

microchip公司的PICPIC18F系列芯片固件

;************************************************************************
;*  Microchip Technology Inc. 2006
;*  Assembler version: 5.06
;*  Filename:
;*	ThreePhaseEngine11.asm (main routine)
;*  Dependents:
;*  None
;*  05/14/2007
;*  Designed to run at 40MHz
;*
;* NOTE: set tab to 8 spaces for proper viewing of this file.
;*
;*  Pinout:
;*                ICD2_1      PIC18F2520
;*                   |  +---------------------+
;*   +5V -- 4.7kohm -+--| MCLR*       PGD/RB7 |-- ICD2_4
;*          PLL_VCOIN --| RA0/AN0     PGC/RB6 |-- ICD2_5
;*            PLL_CLD --| RA1/AN1         RB5 |-- MPU_ADC_CSA (Note 1)
;*             MUX_S1 --| RA2             RB4 |-- MPU_ADC_CSB (Note 1)
;*             MUX_S2 --| RA3             RB3 |-- MPU_ADC_CSC (Note 1)
;*                    --| RA4             RB2 |-- 3909_NEG(TSDO)_PHA (Note 2)
;*         3909_MCLR* --| RA5             RB1 |-- 3909_G1
;*                GND --| VSS        INT0/RB0 |-- 3909_G0
;*        40 MHz XTAL --| OSC1            VDD |-- +5V -- ICD2_2
;*                 +----| OSC2            VSS |-- GND -- ICD2_3
;*(Note 3) PLL_VCOOUT --| RC0/T1CKI    RX/RC7 |-- MPU_RX
;*(Note 3) PLL_COMPIN --| RC1/CCP2     TX/RC6 |-- MPU_TX
;*           CF_PULSE --| RC2        SDO1/RC5 |-- 3909_F1(TSDI)
;*       MPU_ADC_SCLK --| RC3/SCK1   SDI1/RC4 |-- MPU_ADC_SDI (Note 1)
;*                      +---------------------+
;*
;* Notes:
;*    1. The SPI SDI input (SDI1/RC4) is driven by one of the three
;*       MCP3909 NEG(TSDO) outputs--whichever has the F0(CS*) signal
;*       low. When entering test mode, all three chip selects must be LOW.
;*       This is fine because all the SDO outputs will be low at that
;*       point, but this is true only during test mode entry.
;*
;*    2. The 3909_NEG(TSDO)_PHA connection enables the micro to see
;*       the data ready pulse on one of the three MCP3909s. This pulse
;*       starts timer 2. After timer 2 elapses, data can be read via
;*       the SPI. This works for all three MCP3909s because they all
;*       entered test mode 4 at the same time and run off the same clock.
;*
;*    3. Timer 1 runs off the PLL VCO output, which is connected to
;*       T1CKI. Using this timer and the capture/compare/pwm module 2,
;*       the VCO output is divided by 32,768 and the resulting signal
;*       comes out on RC1/CCP2.
;* 
;************************************************************************


	list		p=18F2520
	#include	p18F2520.inc

	CONFIG DEBUG = OFF, WDT = OFF, WDTPS = 32768
	CONFIG LVP = OFF, PBADEN = OFF, MCLRE = ON, LPT1OSC = OFF, XINST=OFF
	CONFIG FCMEN = OFF, IESO = OFF, OSC = HS, CCP2MX = PORTC, STVREN=ON
	CONFIG CP0 = OFF, CP1 = OFF, CP2 = OFF, CP3 = OFF, CPB = OFF
	CONFIG CPD = OFF, WRT0 = OFF, WRT1 = OFF, WRT2 = OFF, WRT3 = OFF, WRTB = OFF
	CONFIG WRTC = OFF, WRTD = OFF, EBTR0 = OFF, EBTR1 = OFF, EBTR2 = OFF, EBTR3 = OFF, EBTRB = OFF

	errorlevel	-302

#define PLL_PRESENT		1		; Comment this out if not using PLL
#define ADC_MCP3909		1		; Comment out if MCP3905
#define REVA1_SILICON		1		; Comment out if PIC18F2520 silicon is other than rev A1

#define	PLL_CLD			PORTA,1		; PLL lock detect from PLL
#define	PLL_CLD_dir		TRISA,1	

#define	MUX_S1			LATA,2		; Multiplexer selector 1
#define	MUX_S1_dir		TRISA,2	
#define	MUX_S2			LATA,3		; Multiplexer selector 2
#define	MUX_S2_dir		TRISA,3	

#define	MPU_ADC_CSA		LATB,5		; Chip select for MCP3909 phase A on RB3
#define	MPU_ADC_CSA_dir		TRISB,5	
#define	MPU_ADC_CSB		LATB,4		; Chip select for MCP3909 phase B on RB2
#define	MPU_ADC_CSB_dir		TRISB,4	
#define	MPU_ADC_CSC		LATB,3		; Chip select for MCP3909 phase C on RB1
#define	MPU_ADC_CSC_dir		TRISB,3	

#define	MCP3909_G0		LATB,0		; Gain selection G0 for all three MCP3909s
#define	MCP3909_G0_dir		TRISB,0	
#define	MCP3909_G1		LATB,1		; Gain selection G1 for all three MCP3909s
#define	MCP3909_G1_dir		TRISB,1	
#define MCP3909_MCLR		LATA,5		; MCLR for all three MCP3909s
#define MCP3909_MCLR_dir	TRISA,5

#define MCP3909_TSDO_PHA	LATB,2		; TSDO from MCP3909 phase A
#define MCP3909_TSDO_PHA_dir	TRISB,2

#define SPI_SDO1		LATC,5		; SPI output
#define SPI_SDO1_dir		TRISC,5
#define SPI_SDI1		LATC,4		; SPI input
#define SPI_SDI1_dir		TRISC,4
#define SPI_SCK1		LATC,3		; SPI clock
#define SPI_SCK1_dir		TRISC,3

#define	CF_PULSE		LATC,2		; CF Pulse
#define	CF_PULSE_dir		TRISC,2	

#define MCP3909_L1_STATE	0x00		; After entering test mode 4, L1 and L0 are low if
						;  value is 0x00 and high if 0xFF

#define TERM_CHAR		'X'		; X is the UART termination character


temp1			EQU	0x00		; General purpose temporary registers...
temp2			EQU	0x01		;  these need to be outside of 
temp3			EQU	0x02

WORKING_BANK		EQU	0x03		; Working bank, must be located 0x00 to 0x7F for A access

Flags1			EQU	0x03		; General flags
;----Begin Bits----
CycleComplete		EQU	0x00		; Set true when line cycle is complete (128 samples)
NewLCGroupStart		EQU	0x01		; When high, indicates start of new LINE_CYC group for EveryLineCycle routines
PhA_Delay_SignBit	EQU	0x02		; Sign bit of PHA_DELAY when PhA_DelayX2 set
PhB_Delay_SignBit	EQU	0x03		; Sign bit of PHB_DELAY when PhB_DelayX2 set
PhC_Delay_SignBit	EQU	0x04		; Sign bit of PHC_DELAY when PhC_DelayX2 set
PLLPhaseLock		EQU	0x05		; Gets set in interrupt routine if PLL Lock detect is HIGH
CalMode			EQU	0x06		; Calibration mode is active
DummyVal		EQU	0x07		; High if dummy value is to be used for simulated calibration
;----End Bits----

CommFlags		EQU	0x04		; UART communication flags
;----Begin Bits----
RCDone			EQU	0x00		; High if comm buffer reception is complete
TXInProgress		EQU	0x01		; High if comm buffer transmission in progress
RCOverrun		EQU	0x02		; High if the UART receiver had an overrun
BufOverflow		EQU	0x03		; High if the receive buffer had an overflow
BufOverrun		EQU	0x04		; High if the receive buffer had an overrun
DoClrEnergyWZ		EQU	0x05		; High if ENERGY_W_Z register to be cleared after this read
DoClrEnergyVAZ		EQU	0x06		; High if ENERGY_VA_Z register to be cleared after this read
;----End Bits----

LPI_SaveW		EQU	0x05		; Space to save WREG during low priority interrupt 
LPI_SaveStatus		EQU	0x06		; Space to save STAUTS during low priority interrupt
LPI_SaveBSR		EQU	0x07		; Space to save BSR during low priority interrupt
Timer0Set		EQU	0x08		; Value for TMR0 register during interrupt
SampleCount		EQU	0x09		; Sample count: starts at 0x80 and counts down to 0
LastLineCycCnt		EQU	0x0A		; Saves LINE_CYC from user area for use after line cycle group complete
LineCyclesRem		EQU	0x0B		; Number of line cycles remaining (starts at 2^LINE_CYC, done when it decs to 0)

PhA_DelayX2		EQU	0x0C		; Lower 7-bits of PHA_DELAY correction shifted up 1 bit (bit 0 is zero)
PhB_DelayX2		EQU	0x0D		; Lower 7-bits of PHB_DELAY correction shifted up 1 bit (bit 0 is zero)
PhC_DelayX2		EQU	0x0E		; Lower 7-bits of PHC_DELAY correction shifted up 1 bit (bit 0 is zero)

PhA_V_7_0		EQU	0x10		; Phase A voltage and current
PhA_V_15_8		EQU	0x11
PhA_I_7_0		EQU	0x12
PhA_I_15_8		EQU	0x13
PhA_V_D1_7_0		EQU	0x14		; Phase A voltage and current delayed by one sample
PhA_V_D1_15_8		EQU	0x15
PhA_I_D1_7_0		EQU	0x16
PhA_I_D1_15_8		EQU	0x17
PhA_V_P_7_0		EQU	0x18		; Phase A voltage and current for power calculation
PhA_V_P_15_8		EQU	0x19
PhA_I_P_7_0		EQU	0x1A
PhA_I_P_15_8		EQU	0x1B

PhB_V_7_0		EQU	0x1C		; Phase B voltage and current
PhB_V_15_8		EQU	0x1D
PhB_I_7_0		EQU	0x1E
PhB_I_15_8		EQU	0x1F
PhB_V_D1_7_0		EQU	0x20		; Phase B voltage and current delayed by one sample
PhB_V_D1_15_8		EQU	0x21
PhB_I_D1_7_0		EQU	0x22
PhB_I_D1_15_8		EQU	0x23
PhB_V_P_7_0		EQU	0x24		; Phase B voltage and current for power calculation
PhB_V_P_15_8		EQU	0x25
PhB_I_P_7_0		EQU	0x26
PhB_I_P_15_8		EQU	0x27

PhC_V_7_0		EQU	0x28		; Phase C voltage and current
PhC_V_15_8		EQU	0x29
PhC_I_7_0		EQU	0x2A
PhC_I_15_8		EQU	0x2B
PhC_V_D1_7_0		EQU	0x2C		; Phase C voltage and current delayed by one sample
PhC_V_D1_15_8		EQU	0x2D
PhC_I_D1_7_0		EQU	0x2E
PhC_I_D1_15_8		EQU	0x2F
PhC_V_P_7_0		EQU	0x30		; Phase C voltage and current for power calculation
PhC_V_P_15_8		EQU	0x31
PhC_I_P_7_0		EQU	0x32
PhC_I_P_15_8		EQU	0x33

PhA_V_WAcc_7_0		EQU	0x34		; 40-bit working accumulator for phase A voltage squared
PhA_V_WAcc_15_8		EQU	0x35
PhA_V_WAcc_23_16	EQU	0x36
PhA_V_WAcc_31_24	EQU	0x37
PhA_V_WAcc_39_32	EQU	0x38
PhA_I_WAcc_7_0		EQU	0x39		; 40-bit working accumulator for phase A current squared
PhA_I_WAcc_15_8		EQU	0x3A
PhA_I_WAcc_23_16	EQU	0x3B
PhA_I_WAcc_31_24	EQU	0x3C
PhA_I_WAcc_39_32	EQU	0x3D
PhA_W_WAcc_7_0		EQU	0x3E		; 40-bit working accumulator for phase A real power squared
PhA_W_WAcc_15_8		EQU	0x3F
PhA_W_WAcc_23_16	EQU	0x40
PhA_W_WAcc_31_24	EQU	0x41
PhA_W_WAcc_39_32	EQU	0x42

PhB_V_WAcc_7_0		EQU	0x43		; 40-bit working accumulator for phase B voltage squared
PhB_V_WAcc_15_8		EQU	0x44
PhB_V_WAcc_23_16	EQU	0x45
PhB_V_WAcc_31_24	EQU	0x46
PhB_V_WAcc_39_32	EQU	0x47
PhB_I_WAcc_7_0		EQU	0x48		; 40-bit working accumulator for phase B current squared
PhB_I_WAcc_15_8		EQU	0x49
PhB_I_WAcc_23_16	EQU	0x4A
PhB_I_WAcc_31_24	EQU	0x4B
PhB_I_WAcc_39_32	EQU	0x4C
PhB_W_WAcc_7_0		EQU	0x4D		; 40-bit working accumulator for phase B real power squared
PhB_W_WAcc_15_8		EQU	0x4E
PhB_W_WAcc_23_16	EQU	0x4F
PhB_W_WAcc_31_24	EQU	0x50
PhB_W_WAcc_39_32	EQU	0x51

PhC_V_WAcc_7_0		EQU	0x52		; 40-bit working accumulator for phase C voltage squared
PhC_V_WAcc_15_8		EQU	0x53
PhC_V_WAcc_23_16	EQU	0x54
PhC_V_WAcc_31_24	EQU	0x55
PhC_V_WAcc_39_32	EQU	0x56
PhC_I_WAcc_7_0		EQU	0x57		; 40-bit working accumulator for phase C current squared
PhC_I_WAcc_15_8		EQU	0x58
PhC_I_WAcc_23_16	EQU	0x59
PhC_I_WAcc_31_24	EQU	0x5A
PhC_I_WAcc_39_32	EQU	0x5B
PhC_W_WAcc_7_0		EQU	0x5C		; 40-bit working accumulator for phase C real power squared
PhC_W_WAcc_15_8		EQU	0x5D
PhC_W_WAcc_23_16	EQU	0x5E
PhC_W_WAcc_31_24	EQU	0x5F
PhC_W_WAcc_39_32	EQU	0x60

PhA_I_Abs_WMax		EQU	0x61		; Absolute maximum of phase A current, working register
PhA_V_Abs_WMax		EQU	0x62		; Absolute maximum of phase A voltage, working register
PhB_I_Abs_WMax		EQU	0x63		; Absolute maximum of phase B current, working register
PhB_V_Abs_WMax		EQU	0x64		; Absolute maximum of phase B voltage, working register
PhC_I_Abs_WMax		EQU	0x65		; Absolute maximum of phase C current, working register
PhC_V_Abs_WMax		EQU	0x66		; Absolute maximum of phase C voltage, working register

CF_Inc_7_0		EQU	0x67		; CF increment value, from most recent energy delta
CF_Inc_15_8		EQU	0x68
CF_Inc_23_16		EQU	0x69
CF_Inc_31_24		EQU	0x6A
CF_Acc_7_0		EQU	0x6B		; CF accumulator, CF goes HIGH when accumulator rolls over
CF_Acc_15_8		EQU	0x6C		;  (and is forced LOW when MSB of accumulator goes HIGH
CF_Acc_23_16		EQU	0x6D		;   even if CF_HIGH_TIME_REM has not timed out)
CF_Acc_31_24		EQU	0x6E
CF_HIGH_Time_Rem	EQU	0x6F		; From CF_PULSE_WIDTH, remaining CF HIGH time
CF_HIGH_Time_Rem_Fine	EQU	0x70		; Fine counter, counts from 8 down to 0
CF_Pulse_Width_W	EQU	0x71		; CF pulse width working register

Period_W_7_0		EQU	0x72		; Period of last line cycle in 1.6us clock ticks
Period_W_15_8		EQU	0x73

LPI_Res0		EQU	0x74		; Temporary holding registers for math results in low priority interrupt
LPI_Res1		EQU	0x75
LPI_Res2		EQU	0x76
LPI_Res3		EQU	0x77
LPI_temp1		EQU	0x78		; Temporary register for low priority interrupt routine
LPI_PRODH_Save		EQU	0x79		; Storage for hardware multiplier during interrupts
LPI_PRODL_Save		EQU	0x7A

DelayReg1		EQU	0x7B		; Used in the delay routine to provide time delays
DelayReg2		EQU	0x7C
DelayReg3		EQU	0x7D

WORKING_BANK_END	EQU	0x7F		; End of working bank


FINAL_BANK		EQU	0x80		; Final bank, this bank may be moved

PhA_I_TAcc_7_0		EQU	0x80		; 40-bit temporary accumulated value for phase A voltage squared
PhA_I_TAcc_15_8		EQU	0x81		;  overwritten every line cycle
PhA_I_TAcc_23_16	EQU	0x82
PhA_I_TAcc_31_24	EQU	0x83
PhA_I_TAcc_39_32	EQU	0x84
PhA_V_TAcc_7_0		EQU	0x85		; 40-bit temporary accumulated value for phase A current squared
PhA_V_TAcc_15_8		EQU	0x86		;  overwritten every line cycle
PhA_V_TAcc_23_16	EQU	0x87
PhA_V_TAcc_31_24	EQU	0x88
PhA_V_TAcc_39_32	EQU	0x89

PhB_I_TAcc_7_0		EQU	0x8A		; 40-bit temporary accumulated value for phase B voltage squared
PhB_I_TAcc_15_8		EQU	0x8B		;  overwritten every line cycle
PhB_I_TAcc_23_16	EQU	0x8C
PhB_I_TAcc_31_24	EQU	0x8D
PhB_I_TAcc_39_32	EQU	0x8E
PhB_V_TAcc_7_0		EQU	0x8F		; 40-bit temporary accumulated value for phase B current squared
PhB_V_TAcc_15_8		EQU	0x90		;  overwritten every line cycle
PhB_V_TAcc_23_16	EQU	0x91
PhB_V_TAcc_31_24	EQU	0x92
PhB_V_TAcc_39_32	EQU	0x93

PhC_I_TAcc_7_0		EQU	0x94		; 40-bit temporary accumulated value for phase C voltage squared
PhC_I_TAcc_15_8		EQU	0x95		;  overwritten every line cycle
PhC_I_TAcc_23_16	EQU	0x96
PhC_I_TAcc_31_24	EQU	0x97
PhC_I_TAcc_39_32	EQU	0x98
PhC_V_TAcc_7_0		EQU	0x99		; 40-bit temporary accumulated value for phase C current squared
PhC_V_TAcc_15_8		EQU	0x9A		;  overwritten every line cycle
PhC_V_TAcc_23_16	EQU	0x9B
PhC_V_TAcc_31_24	EQU	0x9C
PhC_V_TAcc_39_32	EQU	0x9D

PhA_I_FAcc_7_0		EQU	0x9E		; 48-bit final accumulated value for phase A voltage squared
PhA_I_FAcc_15_8		EQU	0x9F		;  accumulates over LINE_CYC line cycles
PhA_I_FAcc_23_16	EQU	0xA0
PhA_I_FAcc_31_24	EQU	0xA1
PhA_I_FAcc_39_32	EQU	0xA2
PhA_I_FAcc_47_40	EQU	0xA3
PhA_V_FAcc_7_0		EQU	0xA4		; 48-bit temporary accumulated value for phase A current squared
PhA_V_FAcc_15_8		EQU	0xA5		;  accumulates over LINE_CYC line cycles
PhA_V_FAcc_23_16	EQU	0xA6
PhA_V_FAcc_31_24	EQU	0xA7
PhA_V_FAcc_39_32	EQU	0xA8
PhA_V_FAcc_47_40	EQU	0xA9

PhB_I_FAcc_7_0		EQU	0xAA		; 48-bit temporary accumulated value for phase B voltage squared
PhB_I_FAcc_15_8		EQU	0xAB		;  accumulates over LINE_CYC line cycles
PhB_I_FAcc_23_16	EQU	0xAC
PhB_I_FAcc_31_24	EQU	0xAD
PhB_I_FAcc_39_32	EQU	0xAE
PhB_I_FAcc_47_40	EQU	0xAF
PhB_V_FAcc_7_0		EQU	0xB0		; 48-bit temporary accumulated value for phase B current squared
PhB_V_FAcc_15_8		EQU	0xB1		;  accumulates over LINE_CYC line cycles
PhB_V_FAcc_23_16	EQU	0xB2
PhB_V_FAcc_31_24	EQU	0xB3
PhB_V_FAcc_39_32	EQU	0xB4
PhB_V_FAcc_47_40	EQU	0xB5

PhC_I_FAcc_7_0		EQU	0xB6		; 48-bit temporary accumulated value for phase C voltage squared
PhC_I_FAcc_15_8		EQU	0xB7		;  accumulates over LINE_CYC line cycles
PhC_I_FAcc_23_16	EQU	0xB8
PhC_I_FAcc_31_24	EQU	0xB9
PhC_I_FAcc_39_32	EQU	0xBA
PhC_I_FAcc_47_40	EQU	0xBB
PhC_V_FAcc_7_0		EQU	0xBC		; 48-bit temporary accumulated value for phase C current squared
PhC_V_FAcc_15_8		EQU	0xBD		;  accumulates over LINE_CYC line cycles
PhC_V_FAcc_23_16	EQU	0xBE
PhC_V_FAcc_31_24	EQU	0xBF
PhC_V_FAcc_39_32	EQU	0xC0
PhC_V_FAcc_47_40	EQU	0xC1

PhA_W_FAcc_7_0		EQU	0xC2		; 40-bit final accumulated value for phase A real power squared
PhA_W_FAcc_15_8		EQU	0xC3		;  overwritten every line cycle
PhA_W_FAcc_23_16	EQU	0xC4
PhA_W_FAcc_31_24	EQU	0xC5
PhA_W_FAcc_39_32	EQU	0xC6

PhB_W_FAcc_7_0		EQU	0xC7		; 40-bit final accumulated value for phase B real power squared
PhB_W_FAcc_15_8		EQU	0xC8		;  overwritten every line cycle
PhB_W_FAcc_23_16	EQU	0xC9
PhB_W_FAcc_31_24	EQU	0xCA
PhB_W_FAcc_39_32	EQU	0xCB

PhC_W_FAcc_7_0		EQU	0xCC		; 40-bit final accumulated value for phase C real power squared