📄 cc1100.lst.svn-base
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129 0x59, // FSTEST Frequency synthesizer calibration.
130 0x81, // TEST2 Various test settings.
131 0x35, // TEST1 Various test settings.
132 0x09, // TEST0 Various test settings.
133 0x0B, // IOCFG2 GDO2 output pin configuration.
134 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
135
136 0x04, // PKTCTRL1 Packet automation control.
137 0x05, // PKTCTRL0 Packet automation control.
138 0x00, // ADDR Device address.
139 0x0c // PKTLEN Packet length.
140 };
141 */
142
143 // 100k E
144 const RF_SETTINGS rfSettings = {
145 0x00,
146 0x08, // FSCTRL1 Frequency synthesizer control.
147 0x00, // FSCTRL0 Frequency synthesizer control.
148 0x10, // FREQ2 Frequency control word, high byte.
149 0xA7, // FREQ1 Frequency control word, middle byte.
150 0x62, // FREQ0 Frequency control word, low byte.
151 0x5B, // MDMCFG4 Modem configuration.
152 0xF8, // MDMCFG3 Modem configuration.
153 0x03, // MDMCFG2 Modem configuration.
154 0x22, // MDMCFG1 Modem configuration.
155 0xF8, // MDMCFG0 Modem configuration.
156
157 0x00, // CHANNR Channel number.
158 0x47, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
159 0xB6, // FREND1 Front end RX configuration.
160 0x10, // FREND0 Front end RX configuration.
161 0x18, // MCSM0 Main Radio Control State Machine configuration.
162 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
163 0x1C, // BSCFG Bit synchronization Configuration.
164 0xC7, // AGCCTRL2 AGC control.
165 0x00, // AGCCTRL1 AGC control.
166 0xB2, // AGCCTRL0 AGC control.
167
168 0xEA, // FSCAL3 Frequency synthesizer calibration.
169 0x2A, // FSCAL2 Frequency synthesizer calibration.
170 0x00, // FSCAL1 Frequency synthesizer calibration.
171 0x11, // FSCAL0 Frequency synthesizer calibration.
172 0x59, // FSTEST Frequency synthesizer calibration.
173 0x81, // TEST2 Various test settings.
174 0x35, // TEST1 Various test settings.
175 0x09, // TEST0 Various test settings.
176 0x0B, // IOCFG2 GDO2 output pin configuration.
C51 COMPILER V8.02 CC1100 10/24/2007 17:21:20 PAGE 4
177 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
178
179 0x04, // PKTCTRL1 Packet automation control.
180 0x05, // PKTCTRL0 Packet automation control.
181 0x00, // ADDR Device address.
182 0x0c // PKTLEN Packet length.
183 };
184 //------------------------------------------------------------------------------------------------------
185 // Chipcon
186 // Product = CC1100
187 // Chip version = E
188 // Crystal accuracy = 40 ppm
189 // X-tal frequency = 26 MHz
190 // RF output power = 0 dBm
191 // RX filterbandwidth = 540.000000 kHz
192 // Deviation = 0.000000
193 // Datarate = 250.000000 kbps
194 // Modulation = (7) MSK
195 // Manchester enable = (0) Manchester disabled
196 // RF Frequency = 433.000000 MHz
197 // Channel spacing = 199.951172 kHz
198 // Channel number = 0
199 // Optimization = Sensitivity
200 // Sync mode = (3) 30/32 sync word bits detected
201 // Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
202 // CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
203 // Forward Error Correction = (0) FEC disabled
204 // Length configuration = (1) Variable length packets, packet length configured by the first received byte
- after sync word.
205 // Packetlength = 255
206 // Preamble count = (2) 4 bytes
207 // Append status = 1
208 // Address check = (11) No address check
209 // FIFO autoflush = 0
210 // Device address = 0
211 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
- of the packet
212 // GDO2 signal selection = (11) Serial Clock
213 /*
214 const RF_SETTINGS rfSettings = {
215 0x00,
216
217 0x0B, // FSCTRL1 Frequency synthesizer control.
218 0x00, // FSCTRL0 Frequency synthesizer control.
219 0x10, // FREQ2 Frequency control word, high byte.
220 0xA7, // FREQ1 Frequency control word, middle byte.
221 0x62, // FREQ0 Frequency control word, low byte.
222 //250k
223 0x2D, // MDMCFG4 Modem configuration.
224 0x3B, // MDMCFG3 Modem configuration.
225 0x73, // MDMCFG2 Modem configuration.
226 0x22, // MDMCFG1 Modem configuration.
227 0xF8, // MDMCFG0 Modem configuration.
228
229 // 1.2k
230 0xF5, //MDMCFG4 (x)
231 0x83, //MDMCFG3 (x)
232 0x03, //MDMCFG2 (x)
233 0x22, //MDMCFG1 (x)
234 0xF8, //MDMCFG0 (x)
235
C51 COMPILER V8.02 CC1100 10/24/2007 17:21:20 PAGE 5
236 0x00, // CHANNR Channel number.
237
238 //0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
239 0x15, //DEVIATN (x)
240 0xB6, // FREND1 Front end RX configuration.
241 0x10, // FREND0 Front end RX configuration.
242 0x18, // MCSM0 Main Radio Control State Machine configuration.
243 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
244 0x1C, // BSCFG Bit synchronization Configuration.
245 0xC7, // AGCCTRL2 AGC control.
246 0x00, // AGCCTRL1 AGC control.
247 0xB2, // AGCCTRL0 AGC control.
248
249 0xEA, // FSCAL3 Frequency synthesizer calibration.
250 0x0A, // FSCAL2 Frequency synthesizer calibration.
251 0x00, // FSCAL1 Frequency synthesizer calibration.
252 0x11, // FSCAL0 Frequency synthesizer calibration.
253 0x59, // FSTEST Frequency synthesizer calibration.
254 0x88, // TEST2 Various test settings.
255 0x31, // TEST1 Various test settings.
256 0x0B, // TEST0 Various test settings.
257 0x0B, // IOCFG2 GDO2 output pin configuration.
258 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
259
260 0x04, // PKTCTRL1 Packet automation control.
261 //0x05, // PKTCTRL1 Packet automation control. //地址检测
262 0x45, // PKTCTRL0 Packet automation control. //可变长数据包,通过同步词汇后的第一个位置配置数据包长⌨️ 快捷键说明
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