📄 miaobiao.vhd
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LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY miaobiao ISPORT(CLK,EN,RESET :IN STD_LOGIC; --时钟频率要求100HZ SEC01L,SEC01R :OUT INTEGER RANGE 0 TO 9; --0.01秒的左右显示位 SECL, SECR :OUT INTEGER RANGE 0 TO 9; --秒的左右显示位 MINL ,MINR :OUT INTEGER RANGE 0 TO 9 --分的左右显示位 );END ENTITY miaobiao;ARCHITECTURE ART OF miaobiao IS SIGNAL SEC01T:INTEGER RANGE 0 TO 99; SIGNAL SECT :INTEGER RANGE 0 TO 59; SIGNAL MINT :INTEGER RANGE 0 TO 59; BEGIN PROCESS(CLK,EN,RESET) IS BEGIN IF(RESET='1') THEN SEC01T<=0; SECT <=0; MINT <=0; ELSIF(CLK'EVENT AND CLK='1')THEN IF(EN='1') THEN IF(SECT=59 AND SEC01T=99) THEN SEC01T<=0; SECT<=0; MINT<=MINT+1; ELSIF(SEC01T=99) THEN SEC01T<=0; SECT<=SECT+1; MINT<=MINT; ELSE SEC01T<=SEC01T+1; SECT<=SECT; MINT<=MINT; END IF; END IF; END IF; END PROCESS; SEC01L<=SEC01T /10; SEC01R<=SEC01T REM 10; SECL<=SECT /10; SECR<=SECT REM 10; MINL<=MINT /10; MINR<=MINT REM 10;END ARCHITECTURE ART;
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