topmiaobiao.map.qmsg

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 17 20:26:00 2008 " "Info: Processing started: Thu Apr 17 20:26:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TopMiaobiao -c TopMiaobiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TopMiaobiao -c TopMiaobiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TopMiaobiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file TopMiaobiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 TopMiaobiao-ART " "Info: Found design unit 1: TopMiaobiao-ART" {  } { { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 TopMiaobiao " "Info: Found entity 1: TopMiaobiao" {  } { { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Display-ART " "Info: Found design unit 1: Display-ART" {  } { { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Display " "Info: Found entity 1: Display" {  } { { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "miaobiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file miaobiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 miaobiao-ART " "Info: Found design unit 1: miaobiao-ART" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 miaobiao " "Info: Found entity 1: miaobiao" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TopMiaobiao " "Info: Elaborating entity \"TopMiaobiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "miaobiao miaobiao:MiaoBContr " "Info: Elaborating entity \"miaobiao\" for hierarchy \"miaobiao:MiaoBContr\"" {  } { { "TopMiaobiao.vhd" "MiaoBContr" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 31 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Display Display:DisSEC01L " "Info: Elaborating entity \"Display\" for hierarchy \"Display:DisSEC01L\"" {  } { { "TopMiaobiao.vhd" "DisSEC01L" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 35 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "miaobiao:MiaoBContr\|MINT\[0\]~552 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"miaobiao:MiaoBContr\|MINT\[0\]~552\"" {  } { { "miaobiao.vhd" "MINT\[0\]~552" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "miaobiao:MiaoBContr\|lpm_counter:MINT_rtl_0 " "Info: Elaborated megafunction instantiation \"miaobiao:MiaoBContr\|lpm_counter:MINT_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "miaobiao:MiaoBContr\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"miaobiao:MiaoBContr\|lpm_divide:Div0\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 41 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_52m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_52m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_52m " "Info: Found entity 1: lpm_divide_52m" {  } { { "db/lpm_divide_52m.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_52m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_ekh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_ekh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_ekh " "Info: Found entity 1: sign_div_unsign_ekh" {  } { { "db/sign_div_unsign_ekh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_ekh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_rke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_rke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_rke " "Info: Found entity 1: alt_u_div_rke" {  } { { "db/alt_u_div_rke.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_rke.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_m9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_m9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_m9c " "Info: Found entity 1: add_sub_m9c" {  } { { "db/add_sub_m9c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_m9c.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_n9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_n9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_n9c " "Info: Found entity 1: add_sub_n9c" {  } { { "db/add_sub_n9c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_n9c.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_o9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_o9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_o9c " "Info: Found entity 1: add_sub_o9c" {  } { { "db/add_sub_o9c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_o9c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_p9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_p9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_p9c " "Info: Found entity 1: add_sub_p9c" {  } { { "db/add_sub_p9c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_p9c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_q9c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_q9c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_q9c " "Info: Found entity 1: add_sub_q9c" {  } { { "db/add_sub_q9c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_q9c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_o5c.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_o5c.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_o5c " "Info: Found entity 1: add_sub_o5c" {  } { { "db/add_sub_o5c.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_o5c.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "miaobiao:MiaoBContr\|lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"miaobiao:MiaoBContr\|lpm_divide:Mod0\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 42 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_bql.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_bql.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_bql " "Info: Found entity 1: lpm_divide_bql" {  } { { "db/lpm_divide_bql.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_bql.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_hkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_hkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_hkh " "Info: Found entity 1: sign_div_unsign_hkh" {  } { { "db/sign_div_unsign_hkh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_hkh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}