miaobiao.map.qmsg

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 16 16:36:17 2008 " "Info: Processing started: Wed Apr 16 16:36:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "miaobiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file miaobiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 miaobiao-ART " "Info: Found design unit 1: miaobiao-ART" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 miaobiao " "Info: Found entity 1: miaobiao" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "miaobiao " "Info: Elaborating entity \"miaobiao\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "f:/altera/quartus60/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Div0\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 41 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_b6m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_b6m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_b6m " "Info: Found entity 1: lpm_divide_b6m" {  } { { "db/lpm_divide_b6m.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_b6m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_akh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_akh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_akh " "Info: Found entity 1: sign_div_unsign_akh" {  } { { "db/sign_div_unsign_akh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_akh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_6pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_6pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_6pe " "Info: Found entity 1: alt_u_div_6pe" {  } { { "db/alt_u_div_6pe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_6pe.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_0ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_0ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_0ec " "Info: Found entity 1: add_sub_0ec" {  } { { "db/add_sub_0ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_0ec.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_1ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_1ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_1ec " "Info: Found entity 1: add_sub_1ec" {  } { { "db/add_sub_1ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_1ec.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_2ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_2ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_2ec " "Info: Found entity 1: add_sub_2ec" {  } { { "db/add_sub_2ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_2ec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3ec " "Info: Found entity 1: add_sub_3ec" {  } { { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4ec " "Info: Found entity 1: add_sub_4ec" {  } { { "db/add_sub_4ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_2ac.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_2ac.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_2ac " "Info: Found entity 1: add_sub_2ac" {  } { { "db/add_sub_2ac.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_2ac.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod0 " "Info: Elaborated megafunction instantiation \"lpm_divide:Mod0\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 42 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hul.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_hul.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hul " "Info: Found entity 1: lpm_divide_hul" {  } { { "db/lpm_divide_hul.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_hul.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_dkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_dkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_dkh " "Info: Found entity 1: sign_div_unsign_dkh" {  } { { "db/sign_div_unsign_dkh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_dkh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_cpe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_cpe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_cpe " "Info: Found entity 1: alt_u_div_cpe" {  } { { "db/alt_u_div_cpe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_cpe.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5ec " "Info: Found entity 1: add_sub_5ec" {  } { { "db/add_sub_5ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_5ec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6ec.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ec.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6ec " "Info: Found entity 1: add_sub_6ec" {  } { { "db/add_sub_6ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_6ec.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5ac.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5ac.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5ac " "Info: Found entity 1: add_sub_5ac" {  } { { "db/add_sub_5ac.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_5ac.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Div1 " "Info: Elaborated megafunction instantiation \"lpm_divide:Div1\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 43 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_a6m.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_a6m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_a6m " "Info: Found entity 1: lpm_divide_a6m" {  } { { "db/lpm_divide_a6m.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_a6m.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Info: Found entity 1: sign_div_unsign_9kh" {  } { { "db/sign_div_unsign_9kh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_9kh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_4pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_4pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_4pe " "Info: Found entity 1: alt_u_div_4pe" {  } { { "db/alt_u_div_4pe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_4pe.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_divide:Mod1 " "Info: Elaborated megafunction instantiation \"lpm_divide:Mod1\"" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 44 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ful.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_ful.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ful " "Info: Found entity 1: lpm_divide_ful" {  } { { "db/lpm_divide_ful.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/lpm_divide_ful.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_bkh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_bkh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_bkh " "Info: Found entity 1: sign_div_unsign_bkh" {  } { { "db/sign_div_unsign_bkh.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/sign_div_unsign_bkh.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_8pe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_8pe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_8pe " "Info: Found entity 1: alt_u_div_8pe" {  } { { "db/alt_u_div_8pe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_8pe.tdf" 34 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4ac.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4ac.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4ac " "Info: Found entity 1: add_sub_4ac" {  } { { "db/add_sub_4ac.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ac.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "298 " "Info: Implemented 298 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "22 " "Info: Implemented 22 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "273 " "Info: Implemented 273 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 16 16:36:25 2008 " "Info: Processing ended: Wed Apr 16 16:36:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}