miaobiao.tan.qmsg

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SEC01R\[2\] SEC01T\[4\] 22.201 ns register " "Info: tco from clock \"CLK\" to destination pin \"SEC01R\[2\]\" through register \"SEC01T\[4\]\" is 22.201 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.062 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.062 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 19 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.692 ns) + CELL(0.542 ns) 3.062 ns SEC01T\[4\] 2 REG LC_X14_Y19_N8 14 " "Info: 2: + IC(1.692 ns) + CELL(0.542 ns) = 3.062 ns; Loc. = LC_X14_Y19_N8; Fanout = 14; REG Node = 'SEC01T\[4\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.234 ns" { CLK SEC01T[4] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.74 % ) " "Info: Total cell delay = 1.370 ns ( 44.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.692 ns ( 55.26 % ) " "Info: Total interconnect delay = 1.692 ns ( 55.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.062 ns" { CLK SEC01T[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.062 ns" { CLK CLK~out0 SEC01T[4] } { 0.000ns 0.000ns 1.692ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "18.983 ns + Longest register pin " "Info: + Longest register to pin delay is 18.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEC01T\[4\] 1 REG LC_X14_Y19_N8 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y19_N8; Fanout = 14; REG Node = 'SEC01T\[4\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SEC01T[4] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.451 ns) 1.751 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1 2 COMB LC_X13_Y17_N7 1 " "Info: 2: + IC(1.300 ns) + CELL(0.451 ns) = 1.751 ns; Loc. = LC_X13_Y17_N7; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[1\]~COUTCOUT1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.751 ns" { SEC01T[4] lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 2.116 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~39 3 COMB LC_X13_Y17_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.365 ns) = 2.116 ns; Loc. = LC_X13_Y17_N8; Fanout = 2; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~39'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.341 ns) 2.929 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~36COUT1_41 4 COMB LC_X14_Y17_N1 2 " "Info: 4: + IC(0.472 ns) + CELL(0.341 ns) = 2.929 ns; Loc. = LC_X14_Y17_N1; Fanout = 2; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~36COUT1_41'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.813 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.989 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~34COUT1 5 COMB LC_X14_Y17_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.989 ns; Loc. = LC_X14_Y17_N2; Fanout = 2; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~34COUT1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 3.049 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~30COUT1_42 6 COMB LC_X14_Y17_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 3.049 ns; Loc. = LC_X14_Y17_N3; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~30COUT1_42'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 3.414 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~31 7 COMB LC_X14_Y17_N4 9 " "Info: 7: + IC(0.000 ns) + CELL(0.365 ns) = 3.414 ns; Loc. = LC_X14_Y17_N4; Fanout = 9; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_3ec:add_sub_3\|add_sub_cella\[2\]~31'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 } "NODE_NAME" } } { "db/add_sub_3ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_3ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.061 ns) + CELL(0.366 ns) 4.841 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[22\]~47 8 COMB LC_X13_Y16_N6 3 " "Info: 8: + IC(1.061 ns) + CELL(0.366 ns) = 4.841 ns; Loc. = LC_X13_Y16_N6; Fanout = 3; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[22\]~47'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.427 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 } "NODE_NAME" } } { "db/alt_u_div_cpe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_cpe.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.451 ns) 6.320 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~50COUT1 9 COMB LC_X12_Y19_N1 2 " "Info: 9: + IC(1.028 ns) + CELL(0.451 ns) = 6.320 ns; Loc. = LC_X12_Y19_N1; Fanout = 2; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~50COUT1'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.479 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 } "NODE_NAME" } } { "db/add_sub_4ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.380 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~48COUT1_57 10 COMB LC_X12_Y19_N2 2 " "Info: 10: + IC(0.000 ns) + CELL(0.060 ns) = 6.380 ns; Loc. = LC_X12_Y19_N2; Fanout = 2; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~48COUT1_57'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 } "NODE_NAME" } } { "db/add_sub_4ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 6.440 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~46COUT1_58 11 COMB LC_X12_Y19_N3 1 " "Info: 11: + IC(0.000 ns) + CELL(0.060 ns) = 6.440 ns; Loc. = LC_X12_Y19_N3; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~46COUT1_58'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 } "NODE_NAME" } } { "db/add_sub_4ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 6.805 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~43 12 COMB LC_X12_Y19_N4 12 " "Info: 12: + IC(0.000 ns) + CELL(0.365 ns) = 6.805 ns; Loc. = LC_X12_Y19_N4; Fanout = 12; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_4ec:add_sub_4\|add_sub_cella\[2\]~43'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 } "NODE_NAME" } } { "db/add_sub_4ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_4ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.280 ns) 8.420 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[32\]~37 13 COMB LC_X14_Y17_N8 3 " "Info: 13: + IC(1.335 ns) + CELL(0.280 ns) = 8.420 ns; Loc. = LC_X14_Y17_N8; Fanout = 3; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[32\]~37'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.615 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 } "NODE_NAME" } } { "db/alt_u_div_cpe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_cpe.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.451 ns) 10.138 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_5ec:add_sub_5\|add_sub_cella\[2\]~58COUT1_71 14 COMB LC_X13_Y19_N5 1 " "Info: 14: + IC(1.267 ns) + CELL(0.451 ns) = 10.138 ns; Loc. = LC_X13_Y19_N5; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_5ec:add_sub_5\|add_sub_cella\[2\]~58COUT1_71'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.718 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 } "NODE_NAME" } } { "db/add_sub_5ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_5ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 10.503 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_5ec:add_sub_5\|add_sub_cella\[2\]~53 15 COMB LC_X13_Y19_N6 11 " "Info: 15: + IC(0.000 ns) + CELL(0.365 ns) = 10.503 ns; Loc. = LC_X13_Y19_N6; Fanout = 11; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_5ec:add_sub_5\|add_sub_cella\[2\]~53'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 } "NODE_NAME" } } { "db/add_sub_5ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_5ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.051 ns) + CELL(0.075 ns) 11.629 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[37\]~801 16 COMB LC_X13_Y17_N9 4 " "Info: 16: + IC(1.051 ns) + CELL(0.075 ns) = 11.629 ns; Loc. = LC_X13_Y17_N9; Fanout = 4; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[37\]~801'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.126 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 } "NODE_NAME" } } { "db/alt_u_div_cpe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_cpe.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.110 ns) + CELL(0.443 ns) 13.182 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~68 17 COMB LC_X13_Y20_N3 1 " "Info: 17: + IC(1.110 ns) + CELL(0.443 ns) = 13.182 ns; Loc. = LC_X13_Y20_N3; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~68'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.553 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 } "NODE_NAME" } } { "db/add_sub_6ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_6ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 13.312 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~76 18 COMB LC_X13_Y20_N4 1 " "Info: 18: + IC(0.000 ns) + CELL(0.130 ns) = 13.312 ns; Loc. = LC_X13_Y20_N4; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~76'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.130 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 } "NODE_NAME" } } { "db/add_sub_6ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_6ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 13.761 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~63 19 COMB LC_X13_Y20_N7 3 " "Info: 19: + IC(0.000 ns) + CELL(0.449 ns) = 13.761 ns; Loc. = LC_X13_Y20_N7; Fanout = 3; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|add_sub_6ec:add_sub_6\|add_sub_cella\[2\]~63'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.449 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 } "NODE_NAME" } } { "db/add_sub_6ec.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/add_sub_6ec.tdf" 32 15 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.183 ns) 14.506 ns lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[44\]~800 20 COMB LC_X13_Y20_N8 1 " "Info: 20: + IC(0.562 ns) + CELL(0.183 ns) = 14.506 ns; Loc. = LC_X13_Y20_N8; Fanout = 1; COMB Node = 'lpm_divide:Mod0\|lpm_divide_hul:auto_generated\|sign_div_unsign_dkh:divider\|alt_u_div_cpe:divider\|StageOut\[44\]~800'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.745 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 } "NODE_NAME" } } { "db/alt_u_div_cpe.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_cpe.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.073 ns) + CELL(2.404 ns) 18.983 ns SEC01R\[2\] 21 PIN PIN_J16 0 " "Info: 21: + IC(2.073 ns) + CELL(2.404 ns) = 18.983 ns; Loc. = PIN_J16; Fanout = 0; PIN Node = 'SEC01R\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.477 ns" { lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 SEC01R[2] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.724 ns ( 40.69 % ) " "Info: Total cell delay = 7.724 ns ( 40.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.259 ns ( 59.31 % ) " "Info: Total interconnect delay = 11.259 ns ( 59.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.983 ns" { SEC01T[4] lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 SEC01R[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "18.983 ns" { SEC01T[4] lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 SEC01R[2] } { 0.000ns 1.300ns 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 1.061ns 1.028ns 0.000ns 0.000ns 0.000ns 1.335ns 1.267ns 0.000ns 1.051ns 1.110ns 0.000ns 0.000ns 0.562ns 2.073ns } { 0.000ns 0.451ns 0.365ns 0.341ns 0.060ns 0.060ns 0.365ns 0.366ns 0.451ns 0.060ns 0.060ns 0.365ns 0.280ns 0.451ns 0.365ns 0.075ns 0.443ns 0.130ns 0.449ns 0.183ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.062 ns" { CLK SEC01T[4] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.062 ns" { CLK CLK~out0 SEC01T[4] } { 0.000ns 0.000ns 1.692ns } { 0.000ns 0.828ns 0.542ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "18.983 ns" { SEC01T[4] lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 SEC01R[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "18.983 ns" { SEC01T[4] lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[1]~COUTCOUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~39 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~36COUT1_41 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~34COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~30COUT1_42 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~31 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[22]~47 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~50COUT1 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~48COUT1_57 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~46COUT1_58 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[32]~37 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~58COUT1_71 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_5ec:add_sub_5|add_sub_cella[2]~53 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[37]~801 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~68 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~76 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|add_sub_6ec:add_sub_6|add_sub_cella[2]~63 lpm_divide:Mod0|lpm_divide_hul:auto_generated|sign_div_unsign_dkh:divider|alt_u_div_cpe:divider|StageOut[44]~800 SEC01R[2] } { 0.000ns 1.300ns 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 1.061ns 1.028ns 0.000ns 0.000ns 0.000ns 1.335ns 1.267ns 0.000ns 1.051ns 1.110ns 0.000ns 0.000ns 0.562ns 2.073ns } { 0.000ns 0.451ns 0.365ns 0.341ns 0.060ns 0.060ns 0.365ns 0.366ns 0.451ns 0.060ns 0.060ns 0.365ns 0.280ns 0.451ns 0.365ns 0.075ns 0.443ns 0.130ns 0.449ns 0.183ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "SEC01T\[5\] EN CLK -2.823 ns register " "Info: th for register \"SEC01T\[5\]\" (data pin = \"EN\", clock pin = \"CLK\") is -2.823 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.052 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.052 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 19 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.682 ns) + CELL(0.542 ns) 3.052 ns SEC01T\[5\] 2 REG LC_X13_Y15_N9 14 " "Info: 2: + IC(1.682 ns) + CELL(0.542 ns) = 3.052 ns; Loc. = LC_X13_Y15_N9; Fanout = 14; REG Node = 'SEC01T\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.224 ns" { CLK SEC01T[5] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.89 % ) " "Info: Total cell delay = 1.370 ns ( 44.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.682 ns ( 55.11 % ) " "Info: Total interconnect delay = 1.682 ns ( 55.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.052 ns" { CLK SEC01T[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.052 ns" { CLK CLK~out0 SEC01T[5] } { 0.000ns 0.000ns 1.682ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.975 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns EN 1 PIN PIN_AB15 15 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB15; Fanout = 15; PIN Node = 'EN'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.183 ns) + CELL(0.705 ns) 5.975 ns SEC01T\[5\] 2 REG LC_X13_Y15_N9 14 " "Info: 2: + IC(4.183 ns) + CELL(0.705 ns) = 5.975 ns; Loc. = LC_X13_Y15_N9; Fanout = 14; REG Node = 'SEC01T\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.888 ns" { EN SEC01T[5] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.792 ns ( 29.99 % ) " "Info: Total cell delay = 1.792 ns ( 29.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.183 ns ( 70.01 % ) " "Info: Total interconnect delay = 4.183 ns ( 70.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.975 ns" { EN SEC01T[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.975 ns" { EN EN~out0 SEC01T[5] } { 0.000ns 0.000ns 4.183ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.052 ns" { CLK SEC01T[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.052 ns" { CLK CLK~out0 SEC01T[5] } { 0.000ns 0.000ns 1.682ns } { 0.000ns 0.828ns 0.542ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.975 ns" { EN SEC01T[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "5.975 ns" { EN EN~out0 SEC01T[5] } { 0.000ns 0.000ns 4.183ns } { 0.000ns 1.087ns 0.705ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}