miaobiao.tan.qmsg

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register SEC01T\[2\] register SECT\[2\] 226.24 MHz 4.42 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 226.24 MHz between source register \"SEC01T\[2\]\" and destination register \"SECT\[2\]\" (period= 4.42 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.253 ns + Longest register register " "Info: + Longest register to register delay is 4.253 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEC01T\[2\] 1 REG LC_X13_Y19_N7 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y19_N7; Fanout = 13; REG Node = 'SEC01T\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SEC01T[2] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.366 ns) 0.909 ns Equal1~59 2 COMB LC_X12_Y19_N9 1 " "Info: 2: + IC(0.543 ns) + CELL(0.366 ns) = 0.909 ns; Loc. = LC_X12_Y19_N9; Fanout = 1; COMB Node = 'Equal1~59'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.909 ns" { SEC01T[2] Equal1~59 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.075 ns) 1.943 ns Equal1~60 3 COMB LC_X13_Y18_N0 10 " "Info: 3: + IC(0.959 ns) + CELL(0.075 ns) = 1.943 ns; Loc. = LC_X13_Y18_N0; Fanout = 10; COMB Node = 'Equal1~60'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.034 ns" { Equal1~59 Equal1~60 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.311 ns) + CELL(0.341 ns) 2.595 ns Add1~91COUT1_103 4 COMB LC_X13_Y18_N1 2 " "Info: 4: + IC(0.311 ns) + CELL(0.341 ns) = 2.595 ns; Loc. = LC_X13_Y18_N1; Fanout = 2; COMB Node = 'Add1~91COUT1_103'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.652 ns" { Equal1~60 Add1~91COUT1_103 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.655 ns Add1~93COUT1_104 5 COMB LC_X13_Y18_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.655 ns; Loc. = LC_X13_Y18_N2; Fanout = 2; COMB Node = 'Add1~93COUT1_104'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { Add1~91COUT1_103 Add1~93COUT1_104 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.365 ns) 3.020 ns Add1~98 6 COMB LC_X13_Y18_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.365 ns) = 3.020 ns; Loc. = LC_X13_Y18_N3; Fanout = 1; COMB Node = 'Add1~98'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.365 ns" { Add1~93COUT1_104 Add1~98 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.761 ns) 4.253 ns SECT\[2\] 7 REG LC_X14_Y18_N6 13 " "Info: 7: + IC(0.472 ns) + CELL(0.761 ns) = 4.253 ns; Loc. = LC_X14_Y18_N6; Fanout = 13; REG Node = 'SECT\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.233 ns" { Add1~98 SECT[2] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.968 ns ( 46.27 % ) " "Info: Total cell delay = 1.968 ns ( 46.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.285 ns ( 53.73 % ) " "Info: Total interconnect delay = 2.285 ns ( 53.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.253 ns" { SEC01T[2] Equal1~59 Equal1~60 Add1~91COUT1_103 Add1~93COUT1_104 Add1~98 SECT[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.253 ns" { SEC01T[2] Equal1~59 Equal1~60 Add1~91COUT1_103 Add1~93COUT1_104 Add1~98 SECT[2] } { 0.000ns 0.543ns 0.959ns 0.311ns 0.000ns 0.000ns 0.472ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.365ns 0.761ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.061 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 19 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns SECT\[2\] 2 REG LC_X14_Y18_N6 13 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X14_Y18_N6; Fanout = 13; REG Node = 'SECT\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.233 ns" { CLK SECT[2] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK SECT[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 SECT[2] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.062 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.062 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 19 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.692 ns) + CELL(0.542 ns) 3.062 ns SEC01T\[2\] 2 REG LC_X13_Y19_N7 13 " "Info: 2: + IC(1.692 ns) + CELL(0.542 ns) = 3.062 ns; Loc. = LC_X13_Y19_N7; Fanout = 13; REG Node = 'SEC01T\[2\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.234 ns" { CLK SEC01T[2] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.74 % ) " "Info: Total cell delay = 1.370 ns ( 44.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.692 ns ( 55.26 % ) " "Info: Total interconnect delay = 1.692 ns ( 55.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.062 ns" { CLK SEC01T[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.062 ns" { CLK CLK~out0 SEC01T[2] } { 0.000ns 0.000ns 1.692ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK SECT[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 SECT[2] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.062 ns" { CLK SEC01T[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.062 ns" { CLK CLK~out0 SEC01T[2] } { 0.000ns 0.000ns 1.692ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.253 ns" { SEC01T[2] Equal1~59 Equal1~60 Add1~91COUT1_103 Add1~93COUT1_104 Add1~98 SECT[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "4.253 ns" { SEC01T[2] Equal1~59 Equal1~60 Add1~91COUT1_103 Add1~93COUT1_104 Add1~98 SECT[2] } { 0.000ns 0.543ns 0.959ns 0.311ns 0.000ns 0.000ns 0.472ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.365ns 0.761ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK SECT[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 SECT[2] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.062 ns" { CLK SEC01T[2] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.062 ns" { CLK CLK~out0 SEC01T[2] } { 0.000ns 0.000ns 1.692ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "MINT\[1\] EN CLK 4.501 ns register " "Info: tsu for register \"MINT\[1\]\" (data pin = \"EN\", clock pin = \"CLK\") is 4.501 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.552 ns + Longest pin register " "Info: + Longest pin to register delay is 7.552 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns EN 1 PIN PIN_AB15 15 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AB15; Fanout = 15; PIN Node = 'EN'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.055 ns) + CELL(0.366 ns) 6.508 ns MINT\[5\]~5 2 COMB LC_X14_Y18_N9 5 " "Info: 2: + IC(5.055 ns) + CELL(0.366 ns) = 6.508 ns; Loc. = LC_X14_Y18_N9; Fanout = 5; COMB Node = 'MINT\[5\]~5'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.421 ns" { EN MINT[5]~5 } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.705 ns) 7.552 ns MINT\[1\] 3 REG LC_X14_Y18_N0 9 " "Info: 3: + IC(0.339 ns) + CELL(0.705 ns) = 7.552 ns; Loc. = LC_X14_Y18_N0; Fanout = 9; REG Node = 'MINT\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.044 ns" { MINT[5]~5 MINT[1] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 28.58 % ) " "Info: Total cell delay = 2.158 ns ( 28.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.394 ns ( 71.42 % ) " "Info: Total interconnect delay = 5.394 ns ( 71.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.552 ns" { EN MINT[5]~5 MINT[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.552 ns" { EN EN~out0 MINT[5]~5 MINT[1] } { 0.000ns 0.000ns 5.055ns 0.339ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.061 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.061 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns CLK 1 CLK PIN_M20 19 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 19; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.691 ns) + CELL(0.542 ns) 3.061 ns MINT\[1\] 2 REG LC_X14_Y18_N0 9 " "Info: 2: + IC(1.691 ns) + CELL(0.542 ns) = 3.061 ns; Loc. = LC_X14_Y18_N0; Fanout = 9; REG Node = 'MINT\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.233 ns" { CLK MINT[1] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.76 % ) " "Info: Total cell delay = 1.370 ns ( 44.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.691 ns ( 55.24 % ) " "Info: Total interconnect delay = 1.691 ns ( 55.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK MINT[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 MINT[1] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.552 ns" { EN MINT[5]~5 MINT[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "7.552 ns" { EN EN~out0 MINT[5]~5 MINT[1] } { 0.000ns 0.000ns 5.055ns 0.339ns } { 0.000ns 1.087ns 0.366ns 0.705ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.061 ns" { CLK MINT[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "3.061 ns" { CLK CLK~out0 MINT[1] } { 0.000ns 0.000ns 1.691ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}