topmiaobiao.hier_info

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

|TopMiaobiao
CLK => Display:DisMINR.CLK
CLK => Display:DisMINL.CLK
CLK => Display:DisSECR.CLK
CLK => Display:DisSECL.CLK
CLK => Display:DisSEC01R.CLK
CLK => Display:DisSEC01L.CLK
CLK => miaobiao:MiaoBContr.CLK
EN => miaobiao:MiaoBContr.EN
RESET => miaobiao:MiaoBContr.RESET
DisplaySEC01L[0] <= Display:DisSEC01L.Display[0]
DisplaySEC01L[1] <= Display:DisSEC01L.Display[1]
DisplaySEC01L[2] <= Display:DisSEC01L.Display[2]
DisplaySEC01L[3] <= Display:DisSEC01L.Display[3]
DisplaySEC01L[4] <= Display:DisSEC01L.Display[4]
DisplaySEC01L[5] <= Display:DisSEC01L.Display[5]
DisplaySEC01L[6] <= Display:DisSEC01L.Display[6]
DisplaySEC01R[0] <= Display:DisSEC01R.Display[0]
DisplaySEC01R[1] <= Display:DisSEC01R.Display[1]
DisplaySEC01R[2] <= Display:DisSEC01R.Display[2]
DisplaySEC01R[3] <= Display:DisSEC01R.Display[3]
DisplaySEC01R[4] <= Display:DisSEC01R.Display[4]
DisplaySEC01R[5] <= Display:DisSEC01R.Display[5]
DisplaySEC01R[6] <= Display:DisSEC01R.Display[6]
DisplaySECL[0] <= Display:DisSECL.Display[0]
DisplaySECL[1] <= Display:DisSECL.Display[1]
DisplaySECL[2] <= Display:DisSECL.Display[2]
DisplaySECL[3] <= Display:DisSECL.Display[3]
DisplaySECL[4] <= Display:DisSECL.Display[4]
DisplaySECL[5] <= Display:DisSECL.Display[5]
DisplaySECL[6] <= Display:DisSECL.Display[6]
DisplaySECR[0] <= Display:DisSECR.Display[0]
DisplaySECR[1] <= Display:DisSECR.Display[1]
DisplaySECR[2] <= Display:DisSECR.Display[2]
DisplaySECR[3] <= Display:DisSECR.Display[3]
DisplaySECR[4] <= Display:DisSECR.Display[4]
DisplaySECR[5] <= Display:DisSECR.Display[5]
DisplaySECR[6] <= Display:DisSECR.Display[6]
DisplayMINL[0] <= Display:DisMINL.Display[0]
DisplayMINL[1] <= Display:DisMINL.Display[1]
DisplayMINL[2] <= Display:DisMINL.Display[2]
DisplayMINL[3] <= Display:DisMINL.Display[3]
DisplayMINL[4] <= Display:DisMINL.Display[4]
DisplayMINL[5] <= Display:DisMINL.Display[5]
DisplayMINL[6] <= Display:DisMINL.Display[6]
DisplayMINR[0] <= Display:DisMINR.Display[0]
DisplayMINR[1] <= Display:DisMINR.Display[1]
DisplayMINR[2] <= Display:DisMINR.Display[2]
DisplayMINR[3] <= Display:DisMINR.Display[3]
DisplayMINR[4] <= Display:DisMINR.Display[4]
DisplayMINR[5] <= Display:DisMINR.Display[5]
DisplayMINR[6] <= Display:DisMINR.Display[6]


|TopMiaobiao|miaobiao:MiaoBContr
CLK => MINT[0].CLK
CLK => MINT[1].CLK
CLK => MINT[2].CLK
CLK => MINT[3].CLK
CLK => MINT[4].CLK
CLK => MINT[5].CLK
CLK => SECT[0].CLK
CLK => SECT[1].CLK
CLK => SECT[2].CLK
CLK => SECT[3].CLK
CLK => SECT[4].CLK
CLK => SECT[5].CLK
CLK => SEC01T[0].CLK
CLK => SEC01T[1].CLK
CLK => SEC01T[2].CLK
CLK => SEC01T[3].CLK
CLK => SEC01T[4].CLK
CLK => SEC01T[5].CLK
CLK => SEC01T[6].CLK
EN => SEC01T~14.OUTPUTSELECT
EN => SEC01T~15.OUTPUTSELECT
EN => SEC01T~16.OUTPUTSELECT
EN => SEC01T~17.OUTPUTSELECT
EN => SEC01T~18.OUTPUTSELECT
EN => SEC01T~19.OUTPUTSELECT
EN => SEC01T~20.OUTPUTSELECT
EN => SECT~12.OUTPUTSELECT
EN => SECT~13.OUTPUTSELECT
EN => SECT~14.OUTPUTSELECT
EN => SECT~15.OUTPUTSELECT
EN => SECT~16.OUTPUTSELECT
EN => SECT~17.OUTPUTSELECT
EN => MINT~6.OUTPUTSELECT
EN => MINT~7.OUTPUTSELECT
EN => MINT~8.OUTPUTSELECT
EN => MINT~9.OUTPUTSELECT
EN => MINT~10.OUTPUTSELECT
EN => MINT~11.OUTPUTSELECT
RESET => MINT[0].ACLR
RESET => MINT[1].ACLR
RESET => MINT[2].ACLR
RESET => MINT[3].ACLR
RESET => MINT[4].ACLR
RESET => MINT[5].ACLR
RESET => SECT[0].ACLR
RESET => SECT[1].ACLR
RESET => SECT[2].ACLR
RESET => SECT[3].ACLR
RESET => SECT[4].ACLR
RESET => SECT[5].ACLR
RESET => SEC01T[0].ACLR
RESET => SEC01T[1].ACLR
RESET => SEC01T[2].ACLR
RESET => SEC01T[3].ACLR
RESET => SEC01T[4].ACLR
RESET => SEC01T[5].ACLR
RESET => SEC01T[6].ACLR
SEC01L[0] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
SEC01L[1] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
SEC01L[2] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
SEC01L[3] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
SEC01R[0] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
SEC01R[1] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
SEC01R[2] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
SEC01R[3] <= Mod0.DB_MAX_OUTPUT_PORT_TYPE
SECL[0] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
SECL[1] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
SECL[2] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
SECL[3] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
SECR[0] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
SECR[1] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
SECR[2] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
SECR[3] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
MINL[0] <= Div2.DB_MAX_OUTPUT_PORT_TYPE
MINL[1] <= Div2.DB_MAX_OUTPUT_PORT_TYPE
MINL[2] <= Div2.DB_MAX_OUTPUT_PORT_TYPE
MINL[3] <= Div2.DB_MAX_OUTPUT_PORT_TYPE
MINR[0] <= Mod2.DB_MAX_OUTPUT_PORT_TYPE
MINR[1] <= Mod2.DB_MAX_OUTPUT_PORT_TYPE
MINR[2] <= Mod2.DB_MAX_OUTPUT_PORT_TYPE
MINR[3] <= Mod2.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisSEC01L
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisSEC01R
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisSECL
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisSECR
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisMINL
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TopMiaobiao|Display:DisMINR
CLK => Display[0]~reg0.CLK
CLK => Display[1]~reg0.CLK
CLK => Display[2]~reg0.CLK
CLK => Display[3]~reg0.CLK
CLK => Display[4]~reg0.CLK
CLK => Display[5]~reg0.CLK
CLK => Display[6]~reg0.CLK
DATA[0] => Mux0.IN19
DATA[0] => Mux1.IN10
DATA[0] => Mux2.IN10
DATA[0] => Mux3.IN10
DATA[0] => Mux4.IN10
DATA[0] => Mux5.IN19
DATA[0] => Mux6.IN19
DATA[1] => Mux0.IN18
DATA[1] => Mux1.IN9
DATA[1] => Mux2.IN9
DATA[1] => Mux3.IN9
DATA[1] => Mux4.IN9
DATA[1] => Mux5.IN18
DATA[1] => Mux6.IN18
DATA[2] => Mux0.IN17
DATA[2] => Mux1.IN8
DATA[2] => Mux2.IN8
DATA[2] => Mux3.IN8
DATA[2] => Mux4.IN8
DATA[2] => Mux5.IN17
DATA[2] => Mux6.IN17
DATA[3] => Mux0.IN16
DATA[3] => Mux5.IN16
DATA[3] => Mux6.IN16
Display[0] <= Display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[1] <= Display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[2] <= Display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[3] <= Display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[4] <= Display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[5] <= Display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Display[6] <= Display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE