topmiaobiao.tan.qmsg

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } } { "f:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "f:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register miaobiao:MiaoBContr\|SEC01T\[1\] register Display:DisSEC01R\|Display\[5\] 51.02 MHz 19.6 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 51.02 MHz between source register \"miaobiao:MiaoBContr\|SEC01T\[1\]\" and destination register \"Display:DisSEC01R\|Display\[5\]\" (period= 19.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.600 ns + Longest register register " "Info: + Longest register to register delay is 15.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns miaobiao:MiaoBContr\|SEC01T\[1\] 1 REG LC44 152 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC44; Fanout = 152; REG Node = 'miaobiao:MiaoBContr\|SEC01T\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { miaobiao:MiaoBContr|SEC01T[1] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.000 ns miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~868 2 COMB LC102 1 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.000 ns; Loc. = LC102; Fanout = 1; COMB Node = 'miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~868'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { miaobiao:MiaoBContr|SEC01T[1] miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 } "NODE_NAME" } } { "db/alt_u_div_1le.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_1le.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 6.800 ns miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~874 3 COMB LC103 1 " "Info: 3: + IC(0.000 ns) + CELL(0.800 ns) = 6.800 ns; Loc. = LC103; Fanout = 1; COMB Node = 'miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~874'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.800 ns" { miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 } "NODE_NAME" } } { "db/alt_u_div_1le.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_1le.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 9.600 ns miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~842 4 COMB LC104 6 " "Info: 4: + IC(0.000 ns) + CELL(2.800 ns) = 9.600 ns; Loc. = LC104; Fanout = 6; COMB Node = 'miaobiao:MiaoBContr\|lpm_divide:Mod0\|lpm_divide_bql:auto_generated\|sign_div_unsign_hkh:divider\|alt_u_div_1le:divider\|StageOut\[43\]~842'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.800 ns" { miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 } "NODE_NAME" } } { "db/alt_u_div_1le.tdf" "" { Text "D:/StudyVHDL/miaobiao/db/alt_u_div_1le.tdf" 64 10 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 15.600 ns Display:DisSEC01R\|Display\[5\] 5 REG LC38 1 " "Info: 5: + IC(1.000 ns) + CELL(5.000 ns) = 15.600 ns; Loc. = LC38; Fanout = 1; REG Node = 'Display:DisSEC01R\|Display\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns ( 87.18 % ) " "Info: Total cell delay = 13.600 ns ( 87.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 12.82 % ) " "Info: Total interconnect delay = 2.000 ns ( 12.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.600 ns" { miaobiao:MiaoBContr|SEC01T[1] miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "15.600 ns" { miaobiao:MiaoBContr|SEC01T[1] miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 Display:DisSEC01R|Display[5] } { 0.000ns 1.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 0.800ns 2.800ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 61 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 61; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns Display:DisSEC01R\|Display\[5\] 2 REG LC38 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC38; Fanout = 1; REG Node = 'Display:DisSEC01R\|Display\[5\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out Display:DisSEC01R|Display[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 61 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 61; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns miaobiao:MiaoBContr\|SEC01T\[1\] 2 REG LC44 152 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC44; Fanout = 152; REG Node = 'miaobiao:MiaoBContr\|SEC01T\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK miaobiao:MiaoBContr|SEC01T[1] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK miaobiao:MiaoBContr|SEC01T[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out miaobiao:MiaoBContr|SEC01T[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out Display:DisSEC01R|Display[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK miaobiao:MiaoBContr|SEC01T[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out miaobiao:MiaoBContr|SEC01T[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.600 ns" { miaobiao:MiaoBContr|SEC01T[1] miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "15.600 ns" { miaobiao:MiaoBContr|SEC01T[1] miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~868 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~874 miaobiao:MiaoBContr|lpm_divide:Mod0|lpm_divide_bql:auto_generated|sign_div_unsign_hkh:divider|alt_u_div_1le:divider|StageOut[43]~842 Display:DisSEC01R|Display[5] } { 0.000ns 1.000ns 0.000ns 0.000ns 1.000ns } { 0.000ns 5.000ns 0.800ns 2.800ns 5.000ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK Display:DisSEC01R|Display[5] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out Display:DisSEC01R|Display[5] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK miaobiao:MiaoBContr|SEC01T[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out miaobiao:MiaoBContr|SEC01T[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "miaobiao:MiaoBContr\|SEC01T\[0\] EN CLK 7.000 ns register " "Info: tsu for register \"miaobiao:MiaoBContr\|SEC01T\[0\]\" (data pin = \"EN\", clock pin = \"CLK\") is 7.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.500 ns + Longest pin register " "Info: + Longest pin to register delay is 6.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns EN 1 PIN PIN_4 19 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_4; Fanout = 19; PIN Node = 'EN'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.000 ns) 6.500 ns miaobiao:MiaoBContr\|SEC01T\[0\] 2 REG LC47 79 " "Info: 2: + IC(1.000 ns) + CELL(5.000 ns) = 6.500 ns; Loc. = LC47; Fanout = 79; REG Node = 'miaobiao:MiaoBContr\|SEC01T\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.000 ns" { EN miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.500 ns ( 84.62 % ) " "Info: Total cell delay = 5.500 ns ( 84.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 15.38 % ) " "Info: Total interconnect delay = 1.000 ns ( 15.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { EN miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { EN EN~out miaobiao:MiaoBContr|SEC01T[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.000 ns + " "Info: + Micro setup delay of destination is 2.000 ns" {  } { { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 61 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 61; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns miaobiao:MiaoBContr\|SEC01T\[0\] 2 REG LC47 79 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC47; Fanout = 79; REG Node = 'miaobiao:MiaoBContr\|SEC01T\[0\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "miaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/miaobiao.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out miaobiao:MiaoBContr|SEC01T[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.500 ns" { EN miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "6.500 ns" { EN EN~out miaobiao:MiaoBContr|SEC01T[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.500ns 5.000ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK miaobiao:MiaoBContr|SEC01T[0] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out miaobiao:MiaoBContr|SEC01T[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DisplayMINR\[1\] Display:DisMINR\|Display\[1\] 5.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"DisplayMINR\[1\]\" through register \"Display:DisMINR\|Display\[1\]\" is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.500 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns CLK 1 CLK PIN_83 61 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_83; Fanout = 61; CLK Node = 'CLK'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns Display:DisMINR\|Display\[1\] 2 REG LC43 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC43; Fanout = 1; REG Node = 'Display:DisMINR\|Display\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.000 ns" { CLK Display:DisMINR|Display[1] } "NODE_NAME" } } { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK Display:DisMINR|Display[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out Display:DisMINR|Display[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "2.000 ns + " "Info: + Micro clock to output delay of source is 2.000 ns" {  } { { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.500 ns + Longest register pin " "Info: + Longest register to pin delay is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Display:DisMINR\|Display\[1\] 1 REG LC43 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC43; Fanout = 1; REG Node = 'Display:DisMINR\|Display\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Display:DisMINR|Display[1] } "NODE_NAME" } } { "Display.vhd" "" { Text "D:/StudyVHDL/miaobiao/Display.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns DisplayMINR\[1\] 2 PIN PIN_27 0 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'DisplayMINR\[1\]'" {  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Display:DisMINR|Display[1] DisplayMINR[1] } "NODE_NAME" } } { "TopMiaobiao.vhd" "" { Text "D:/StudyVHDL/miaobiao/TopMiaobiao.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 100.00 % ) " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Display:DisMINR|Display[1] DisplayMINR[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Display:DisMINR|Display[1] DisplayMINR[1] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { CLK Display:DisMINR|Display[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { CLK CLK~out Display:DisMINR|Display[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.500ns 0.000ns } } } { "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { Display:DisMINR|Display[1] DisplayMINR[1] } "NODE_NAME" } } { "f:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/altera/quartus60/win/Technology_Viewer.qrui" "1.500 ns" { Display:DisMINR|Display[1] DisplayMINR[1] } { 0.000ns 0.000ns } { 0.000ns 1.500ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}