📄 t_miaobiao.vhd
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LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY t_miaobiao ISEND ENTITY t_miaobiao;ARCHITECTURE ARCT OF t_miaobiao IS COMPONENT miaobiao IS PORT(CLK,EN,RESET:IN STD_LOGIC; SEC01L,SEC01R :OUT INTEGER RANGE 0 TO 9; SECL,MINL:OUT INTEGER RANGE 0 TO 7; SECR,MINR:OUT INTEGER RANGE 0 TO 9 );END COMPONENT miaobiao;SIGNAL CLK,EN,RESET : STD_LOGIC:='0';SIGNAL SEC01L,SEC01R: INTEGER RANGE 0 TO 9;SIGNAL SECL,MINL : INTEGER RANGE 0 TO 7;SIGNAL SECR,MINR : INTEGER RANGE 0 TO 9; BEGIN CLK<=NOT CLK AFTER 5 MS; RESET<='0','1'AFTER 40 MS,'0' AFTER 100 MS; PROCESS BEGIN EN<='0'; WAIT FOR 40 MS; EN<='1'; WAIT FOR 500 MS; EN<='0'; END PROCESS;U1:miaobiao PORT MAP(CLK=>CLK,EN=>EN,RESET=>RESET, SEC01L=>SEC01L,SEC01R=>SEC01R, SECL=>SECL,MINL=>MINL, SECR=>SECR,MINR=>MINR);END ARCHITECTURE ARCT;
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