miaobiao.sim.rpt

实现秒表的功能。能精确到0.01位。最多能计时1个小时。

; Simulator Settings                                                                                                      ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Option                                                                                     ; Setting    ; Default Value ;
+--------------------------------------------------------------------------------------------+------------+---------------+
; Simulation mode                                                                            ; Timing     ; Timing        ;
; Start time                                                                                 ; 0 ns       ; 0 ns          ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; Off        ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      62.72 % ;
; Total nodes checked                                 ; 296          ;
; Total output ports checked                          ; 464          ;
; Total output ports with complete 1/0-value coverage ; 291          ;
; Total output ports with no 1/0-value coverage       ; 163          ;
; Total output ports with no 1-value coverage         ; 167          ;
; Total output ports with no 0-value coverage         ; 169          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                           ; Output Port Name                                                                                                                                            ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_6|add_sub_cella[2]~43 ; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_6|add_sub_cella[2]~43         ; combout          ;
; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_5|add_sub_cella[2]~43 ; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_5|add_sub_cella[2]~43         ; combout          ;
; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43 ; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_4ec:add_sub_4|add_sub_cella[2]~43         ; combout          ;
; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~29 ; |miaobiao|lpm_divide:Div0|lpm_divide_b6m:auto_generated|sign_div_unsign_akh:divider|alt_u_div_6pe:divider|add_sub_3ec:add_sub_3|add_sub_cella[2]~29         ; combout          ;