display.vhd

来自「实现秒表的功能。能精确到0.01位。最多能计时1个小时。」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Display IS
PORT(CLK    :IN  STD_LOGIC;
     DATA   :IN  INTEGER RANGE 0 TO 9;
     Display:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
     );
END ENTITY Display;
ARCHITECTURE ART OF Display IS
 BEGIN
   PROCESS(CLK,DATA)
    BEGIN
      IF(CLK'EVENT AND CLK='1') THEN
        CASE DATA IS
        WHEN 0=>Display<="0111111";
        WHEN 1=>Display<="0110000";
		WHEN 2=>Display<="1101101";
		WHEN 3=>Display<="1111001";
		WHEN 4=>Display<="0110011";
		WHEN 5=>Display<="1011011";
		WHEN 6=>Display<="0011111";
		WHEN 7=>Display<="1110000";
		WHEN 8=>Display<="1111111";
		WHEN 9=>Display<="1110011";
		WHEN OTHERS=>Display<="0000000";
		END CASE;
	  END IF;
	END PROCESS;
END ARCHITECTURE ART;