📄 c8051f126_driver.lst
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C51 COMPILER V8.05a C8051F126_DRIVER 03/27/2008 14:12:42 PAGE 1
C51 COMPILER V8.05a, COMPILATION OF MODULE C8051F126_DRIVER
OBJECT MODULE PLACED IN c8051f126_driver.OBJ
COMPILER INVOKED BY: d:\Keil\C51\BIN\C51.EXE c8051f126_driver.c BROWSE DEBUG OBJECTEXTEND
line level source
1 /************************************************************
2 版权 (C), 2008, 苏州良仪电子研发部.
3 文件名：c8051f126_driver.c
4 作者：申瑞峰 版本：1.0 日期：2008/1/6
5 描述：对c8051f的端口，晶振的初始化
6 功能函数列表：
7 1. SysclkInit() //内部晶振的初始化（24.5MHZ）
8 2. ExternalCrystal(void) //外部晶振的初始化
9 3. PortInit(void) //I/O口初始化
10 历史记录：
11 <作者> <时间> <版本 > <描述>
12 申瑞峰 08/1/6 1.0 build this moudle
13 ***********************************************************/
14 #include <c8051F120.h>
15 #define uchar unsigned char
16 #define uint unsigned int
17
18 #define TIME (0.001)
19 #define PLL_MUL (2) // Sets PLL multiplier N
20 #define PLL_DIV (1) // Sets PLL divider M
21
22 sfr16 RCAP3 = 0xca; // Timer3 capture/reload
23 sfr16 TMR3 = 0xcc; // Timer3
24 //-----------------------------------------------------------------------------
25 // Global Constants
26 //-----------------------------------------------------------------------------
27
28 #define INTOSC (24500000L) // Internal oscillator frequency
29
30 //-----------------------------------------------------------------------------
31 // Macros used to calculate PLL and SYSCLK frequencies
32 //-----------------------------------------------------------------------------
33
34 #define PLL_DIV_CLK (INTOSC/PLL_DIV) // PLL divided clock input frequency
35 #define PLL_OUT_CLK (PLL_DIV_CLK*PLL_MUL)
36 // PLL output frequency
37 #define SYSCLK PLL_OUT_CLK // System clock derived from PLL
38
39 //-----------------------------------------------------------------------------
40 // Macros used to calculate Loop Filter Bits
41 //
42 // Reference
43 // C8051F121x-13x.pdf
44 // SFR Definition 14.8. PLL0FLT: PLL Filter
45 //
46 // Note that PLL Loop filter bits give a suitable frequency range for each
47 // setting. In some cases more than one setting may be acceptable for a
48 // particular frequency. This macro will select the best fit setting for
49 // a particular frequency.
50 //
51 //-----------------------------------------------------------------------------
52
53 #if (PLL_DIV_CLK)<(5000000L)
#error "error: PLL divided clock frequency Too Low!"
#elif (PLL_DIV_CLK)<(8000000L)
C51 COMPILER V8.05a C8051F126_DRIVER 03/27/2008 14:12:42 PAGE 2
#define PLLFLT_LOOP 0x0F
#elif (PLL_DIV_CLK)<(12500000L)
#define PLLFLT_LOOP 0x07
#elif (PLL_DIV_CLK)<(19500000L)
#define PLLFLT_LOOP 0x03
#elif (PLL_DIV_CLK)<(30000001L)
62 #define PLLFLT_LOOP 0x01
63 #else
#error "error: PLL divided clock frequency Too High!"
#endif
66
67 //-----------------------------------------------------------------------------
68 // Macros used to calculate ICO Bits
69 //
70 // Reference
71 // C8051F121x-13x.pdf
72 // SFR Definition 14.8. PLL0FLT: PLL Filter
73 //
74 // Note that PLL ICO bits give a suitable frequency range for each setting.
75 // In some cases more than one setting may be acceptable for a particular
76 // frequency. This macro will select the best fit setting for a particular
77 // frequency.
78 //
79 //-----------------------------------------------------------------------------
80
81 #if (PLL_OUT_CLK)<(25000000L)
#error "error: PLL output frequency Too Low!"
#elif (PLL_OUT_CLK)<(42500000L)
#define PLLFLT_ICO 0x30
#elif (PLL_OUT_CLK)<(52500000L)
86 #define PLLFLT_ICO 0x20
87 #elif (PLL_OUT_CLK)<(72500000L)
#define PLLFLT_ICO 0x10
#elif (PLL_OUT_CLK)<(100000001L)
#define PLLFLT_ICO 0x00
#else
#error "error: PLL output frequency Too High"
#endif
94
95 //-----------------------------------------------------------------------------
96 // Macros used to calculate Flash Read Time Bits
97 //
98 // Reference
99 // C8051F121x-13x.pdf
100 // SFR Definition 15.2. FLSCL: Flash Memory Control
101 //-----------------------------------------------------------------------------
102
103 #if (SYSCLK)<(25000001L)
#define FLSCL_FLRT 0x00
#elif (SYSCLK)<(50000001L)
106 #define FLSCL_FLRT 0x10
107 #elif (SYSCLK)<(50000001L)
#define FLSCL_FLRT 0x20
#elif (SYSCLK)<(100000001L)
#define FLSCL_FLRT 0x30
#else
#error "error: SYSCLK Too High"
#endif
114 /*************************************************
115 函数名: SysclkInit()
116 描述: 内部晶振初始化，内部时钟达到22.1184M
117 扇出数: 无
C51 COMPILER V8.05a C8051F126_DRIVER 03/27/2008 14:12:42 PAGE 3
118 扇入数: Main()
119 输入参数: 无
120 输出参数: 无
121 返回值: 无
122 其他: 无
123 *************************************************/
124 void SysclkInit(void)
125 {
126 1 uchar SFRPAGE_SAVE = SFRPAGE;
127 1 SFRPAGE = CONFIG_PAGE;
128 1 OSCICN = 0X83; //使能内部振荡电路，系统时钟为22.1184M不分频
129 1 RSTSRC = 0X04; //写：时钟丢失检测器使能。如果检测到时钟丢失条件，则触发复位。
130 1 //读：前面的复位来自时钟丢失检测器超时。
131 1 CLKSEL = 0X00; //选择内部时钟为系统时钟
132 1 SFRPAGE = SFRPAGE_SAVE;
133 1 }
134
135 /*************************************************
136 函数名: ExternalCrystal()
137 描述: 外部晶振初始化,外部时钟频率达到24.5M
138 扇出数: 无
139 扇入数: Main()
140 输入参数: 无
141 输出参数: 无
142 返回值: 无
143 其他: 无
144 *************************************************/
145 void ExternalCrystal(void)
146 {
147 1 uint i;
148 1 uchar SFRPAGE_SAVE = SFRPAGE;
149 1 SFRPAGE = CONFIG_PAGE;
150 1 OSCXCN = 0x67; // start external oscillator with
151 1 // 22.1184MHz crystal
152 1 for (i = 13000; i > 0; i--); // wait for osc to start
153 1
154 1 while (!(OSCXCN & 0x80)) ; // Wait for crystal osc. to settle
155 1
156 1 //OSCICN = 0x88; // select external oscillator as SYSCLK
157 1 //CLKSEL = 0x01; // source and enable missing clock
158 1 // detector
159 1 SFRPAGE = SFRPAGE_SAVE;
160 1 }
161
162 /*************************************************
163 函数名: PortInit()
164 描述: I/O口初始化,全局弱上拉，使能交叉开关，打开外部中断0
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