c8051f126_driver.c

c8051120锁相环

/************************************************************
  版权 (C), 2008, 苏州良仪电子研发部.
  文件名：c8051f126_driver.c
  作者：申瑞峰        版本：1.0         日期：2008/1/6
  描述：对c8051f的端口，晶振的初始化    
  功能函数列表：   
    1. SysclkInit()            //内部晶振的初始化（24.5MHZ）
    2. ExternalCrystal(void)   //外部晶振的初始化
    3. PortInit(void)          //I/O口初始化
  历史记录：        
      <作者>        <时间>    <版本 >        <描述>
      申瑞峰        08/1/6     1.0        build this moudle  
***********************************************************/
#include <c8051F120.h>
#define uchar unsigned char
#define uint unsigned int

#define TIME (0.001)
#define PLL_MUL (2)               // Sets PLL multiplier N
#define PLL_DIV (1)               // Sets PLL divider M

sfr16 RCAP3  = 0xca;                 // Timer3 capture/reload
sfr16 TMR3  = 0xcc;                 // Timer3
//-----------------------------------------------------------------------------
// Global Constants
//-----------------------------------------------------------------------------

#define INTOSC       (24500000L)       // Internal oscillator frequency

//-----------------------------------------------------------------------------
// Macros used to calculate PLL and SYSCLK frequencies
//-----------------------------------------------------------------------------

#define PLL_DIV_CLK  (INTOSC/PLL_DIV)  // PLL divided clock input frequency
#define PLL_OUT_CLK  (PLL_DIV_CLK*PLL_MUL)
                                       // PLL output frequency
#define SYSCLK       PLL_OUT_CLK       // System clock derived from PLL

//-----------------------------------------------------------------------------
// Macros used to calculate Loop Filter Bits
//
// Reference
// C8051F121x-13x.pdf 
// SFR Definition 14.8. PLL0FLT: PLL Filter
//
// Note that PLL Loop filter bits give a suitable frequency range for each 
// setting. In some cases more than one setting may be acceptable for a 
// particular frequency. This macro will select the best fit setting for
// a particular frequency. 
//
//-----------------------------------------------------------------------------

#if (PLL_DIV_CLK)<(5000000L)
   #error "error: PLL divided clock frequency Too Low!"
#elif (PLL_DIV_CLK)<(8000000L)
   #define PLLFLT_LOOP 0x0F
#elif (PLL_DIV_CLK)<(12500000L)
   #define PLLFLT_LOOP 0x07
#elif (PLL_DIV_CLK)<(19500000L)
   #define PLLFLT_LOOP 0x03
#elif (PLL_DIV_CLK)<(30000001L)
   #define PLLFLT_LOOP 0x01
#else
   #error "error: PLL divided clock frequency Too High!"
#endif

//-----------------------------------------------------------------------------
// Macros used to calculate ICO  Bits
//
// Reference
// C8051F121x-13x.pdf 
// SFR Definition 14.8. PLL0FLT: PLL Filter
//
// Note that PLL ICO bits give a suitable frequency range for each setting. 
// In some cases more than one setting may be acceptable for a particular 
// frequency. This macro will select the best fit setting for a particular
// frequency. 
//
//-----------------------------------------------------------------------------

#if (PLL_OUT_CLK)<(25000000L)
   #error "error: PLL output frequency Too Low!"
#elif (PLL_OUT_CLK)<(42500000L)
   #define PLLFLT_ICO 0x30
#elif (PLL_OUT_CLK)<(52500000L)
   #define PLLFLT_ICO 0x20
#elif (PLL_OUT_CLK)<(72500000L)
   #define PLLFLT_ICO 0x10
#elif (PLL_OUT_CLK)<(100000001L)
   #define PLLFLT_ICO 0x00
#else
   #error "error: PLL output frequency Too High"
#endif

//-----------------------------------------------------------------------------
// Macros used to calculate  Flash Read Time  Bits
//
// Reference
// C8051F121x-13x.pdf 
// SFR Definition 15.2. FLSCL: Flash Memory Control
//-----------------------------------------------------------------------------

#if (SYSCLK)<(25000001L)
   #define FLSCL_FLRT 0x00
#elif (SYSCLK)<(50000001L)
   #define FLSCL_FLRT 0x10
#elif (SYSCLK)<(50000001L)
   #define FLSCL_FLRT 0x20
#elif (SYSCLK)<(100000001L)
   #define FLSCL_FLRT 0x30
#else
   #error "error: SYSCLK Too High"
#endif
/*************************************************
  函数名:   SysclkInit()
  描述:     内部晶振初始化，内部时钟达到22.1184M
  扇出数:   无
  扇入数:   Main()
  输入参数: 无
  输出参数: 无
  返回值:   无
  其他:     无
*************************************************/
void SysclkInit(void)
{ 
    uchar SFRPAGE_SAVE = SFRPAGE;
    SFRPAGE = CONFIG_PAGE;
    OSCICN = 0X83;                                 //使能内部振荡电路，系统时钟为22.1184M不分频
    RSTSRC = 0X04;                  //写：时钟丢失检测器使能。如果检测到时钟丢失条件，则触发复位。
                                    //读：前面的复位来自时钟丢失检测器超时。 
    CLKSEL = 0X00;                                 //选择内部时钟为系统时钟
    SFRPAGE = SFRPAGE_SAVE; 
}



/*************************************************
  函数名:   PortInit()
  描述:     I/O口初始化,全局弱上拉，使能交叉开关，打开外部中断0
  扇出数:   无
  扇入数:   Main()
  输入参数: 无
  输出参数: 无
  返回值:   无
  其他:     无
*************************************************/
void PortInit(void)
{
    uchar SFRPAGE_SAVE = SFRPAGE;
    SFRPAGE = CONFIG_PAGE;
    XBR0 = 0X00;
    XBR1 = 0X14;                            	  //打开外部中断0
    XBR2 = 0XC0;                                  //全局弱上拉，使能交叉开关，
    P0 = 0XFF;
    P3 = 0XFF;
    P4 = 0xff;
    P5 = 0XFF;
    P6 = 0XFF;
    P7 = 0XFF;
    P0MDOUT = 0X0f;
    P1MDOUT = 0XF8;
    P2MDOUT = 0Xff;
    P3MDOUT = 0Xff;
    P4MDOUT = 0Xff;
    P5MDOUT = 0xff;
    P6MDOUT = 0Xff;
    P7MDOUT = 0Xff;
    SFRPAGE = SFRPAGE_SAVE;
}


/*************************************************
  函数名:   PllIint()
  描述:     锁相环初始化
  扇出数:   无
  扇入数:   Main()
  输入参数: 无
  输出参数: 无
  返回值:   无
  其他:     无
*************************************************/
void PllInit()
{
   unsigned char n;                    // n used for short delay counter

   SFRPAGE = CONFIG_PAGE;              // Set SFR page

   OSCICN = 0x83;                      // Set internal oscillator to run
                                       // at its maximum frequency

   PLL0CN  = 0x00;                     // Set internal oscillator as PLL source

   SFRPAGE = LEGACY_PAGE;
   FLSCL   = FLSCL_FLRT;               // Set FLASH read time according to SYSCLK
   SFRPAGE = CONFIG_PAGE;

   PLL0CN |= 0x01;                     // Enable Power to PLL
   PLL0DIV = PLL_DIV;                  // Set PLL divider value using macro
   PLL0MUL = PLL_MUL;                  // Set PLL multiplier value using macro
   PLL0FLT = PLLFLT_ICO|PLLFLT_LOOP;   // Set the PLL filter loop and ICO bits
   for (n=0xFF;n!=0;n--);              // Wait at least 5us
   PLL0CN  |= 0x02;                    // Enable the PLL
   while(!(PLL0CN & 0x10));            // Wait until PLL frequency is locked
   CLKSEL  = 0x02;                     // Select PLL as SYSCLK source
}

/*************************************************
  函数名:   PllIint()
  描述:     锁相环初始化
  扇出数:   无
  扇入数:   Main()
  输入参数: 无
  输出参数: 无
  返回值:   无
  其他:     无
*************************************************/
void Time3Init()
{
    uchar SFRPAGE_SAVE = SFRPAGE;
    SFRPAGE = TMR3_PAGE;
    TMR3CN = 0X00;
    TMR3CF = 0X08;
    RCAP3 = -(INTOSC / 500);
    TMR3 = RCAP3;
    TR3 = 1;
    EIE2 |= 0X01;
    SFRPAGE = SFRPAGE_SAVE;
}