tlsim.log,1

来自「cadence高速设计那本书用到的设计的例子」· LOG,1 代码 · 共 41 行

 **** Tlsim Version 14.1 ****

 Sun Sep 11 08:55:29 2005

**** Tlsim command line ****
 tlsim -r 0.200000 -o waveforms.sim -dl delay.dl -dst distortion.dst -log tlsim.log -ocycle cycle.msm main.spc


Number of Nodes in this circuit = 39


Statistics on N-line elements:
 Number of 'n' type multi-conductor elements = 8
 Type-of-N-element  #elms Max_Length TotalLength

 1-line-N-elm     8   0.0106858    0.0346959
 Total Interconnect Length = 0.0346959
 Total Coupled Length = 0

 Following is some statistics on Model usage
   Model-Type      Model-Name     Number-of-Models-in-this-circuit

   bdrvr         CDSDefaultOutput_Typ               2 
   bdrvr         CDSDefaultInput_Typ               2 
  No of 'Bdrvr' type model instance = 4

 Time Step at Start = 1.5e-010



 Simulation will start at t=0 and end at t=4.02528e-008. 



 Simulation Complete 


**** Transient Simulation Statistics ****

    Number Of time step solutions = 269