wash.vto

洗衣机的程序 洗衣机的程序

	PORT MAP (Z0 => ZZ_PIN, A0 => B0_X3O);
GLB_B0_P8_xa : PGBUFI
	PORT MAP (Z0 => B0_P8_xa, A0 => B0_P8);
GLB_BUF_1197 : PGBUFI
	PORT MAP (Z0 => BUF_1197, A0 => B0_X1O);
GLB_B0_IN5 : PGBUFI
	PORT MAP (Z0 => B0_IN5, A0 => OR_1116_grp);
GLB_B0_IN7 : PGBUFI
	PORT MAP (Z0 => B0_IN7, A0 => CPX_grp);
GLB_B0_IN13 : PGBUFI
	PORT MAP (Z0 => B0_IN13, A0 => N_15_grp);
GLB_B0_IN11 : PGBUFI
	PORT MAP (Z0 => B0_IN11, A0 => N_14_grp);
GLB_B0_IN4 : PGBUFI
	PORT MAP (Z0 => B0_IN4, A0 => N_12_grp);
GLB_B0_IN15 : PGBUFI
	PORT MAP (Z0 => B0_IN15, A0 => N_17_grp);
GLB_B0_IN6 : PGBUFI
	PORT MAP (Z0 => B0_IN6, A0 => N_13_grp);
GLB_B0_IN14 : PGBUFI
	PORT MAP (Z0 => B0_IN14, A0 => N_16_grp);
GLB_B0_IN12 : PGBUFI
	PORT MAP (Z0 => B0_IN12, A0 => N_11_grp);
GLB_B0_IN9 : PGBUFI
	PORT MAP (Z0 => B0_IN9, A0 => N_10_grp);
GLB_B0_X3O : PGXOR2
	PORT MAP (Z0 => B0_X3O, A1 => B0_X3MO, A0 => B0_G0);
GLB_B0_X1O : PGXOR2
	PORT MAP (Z0 => B0_X1O, A1 => B0_P8_xa, A0 => B0_G2);
GLB_B0_IN11B : PGINVI
	PORT MAP (ZN0 => B0_IN11B, A0 => N_14_grp);
GLB_B0_IN5B : PGINVI
	PORT MAP (ZN0 => B0_IN5B, A0 => OR_1116_grp);
GLB_B0_IN14B : PGINVI
	PORT MAP (ZN0 => B0_IN14B, A0 => N_16_grp);
GLB_B0_IN12B : PGINVI
	PORT MAP (ZN0 => B0_IN12B, A0 => N_11_grp);
GLB_B0_IN9B : PGINVI
	PORT MAP (ZN0 => B0_IN9B, A0 => N_10_grp);
GLB_B0_IN15B : PGINVI
	PORT MAP (ZN0 => B0_IN15B, A0 => N_17_grp);
GLB_B0_IN13B : PGINVI
	PORT MAP (ZN0 => B0_IN13B, A0 => N_15_grp);
GLB_B0_IN6B : PGINVI
	PORT MAP (ZN0 => B0_IN6B, A0 => N_13_grp);
GLB_B0_IN4B : PGINVI
	PORT MAP (ZN0 => B0_IN4B, A0 => N_12_grp);
GLB_B1_P17 : PGAND6
	PORT MAP (Z0 => B1_P17, A5 => B1_IN4B, A4 => B1_IN6B, A3 => B1_IN12B, 
	A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15);
GLB_B1_P16 : PGAND2
	PORT MAP (Z0 => B1_P16, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P15 : PGAND3
	PORT MAP (Z0 => B1_P15, A2 => B1_IN11, A1 => B1_IN13, A0 => B1_IN15B);
GLB_B1_P14 : PGAND4
	PORT MAP (Z0 => B1_P14, A3 => B1_IN11B, A2 => B1_IN13B, A1 => B1_IN14B, 
	A0 => B1_IN15);
GLB_B1_P13 : PGAND4
	PORT MAP (Z0 => B1_P13, A3 => B1_IN4, A2 => B1_IN6, A1 => B1_IN13, 
	A0 => B1_IN15B);
GLB_B1_P12 : PGAND7
	PORT MAP (Z0 => B1_P12, A6 => B1_IN4B, A5 => B1_IN6B, A4 => B1_IN11B, 
	A3 => B1_IN12B, A2 => B1_IN13B, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P11 : PGAND7
	PORT MAP (Z0 => B1_P11, A6 => B1_IN4B, A5 => B1_IN6, A4 => B1_IN11, 
	A3 => B1_IN12, A2 => B1_IN13, A1 => B1_IN14B, A0 => B1_IN15B);
GLB_B1_P10 : PGAND7
	PORT MAP (Z0 => B1_P10, A6 => B1_IN4, A5 => B1_IN6, A4 => B1_IN11, 
	A3 => B1_IN12, A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15B);
GLB_B1_P9 : PGAND7
	PORT MAP (Z0 => B1_P9, A6 => B1_IN4B, A5 => B1_IN6, A4 => B1_IN11, 
	A3 => B1_IN12B, A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15B);
GLB_B1_P8 : PGAND7
	PORT MAP (Z0 => B1_P8, A6 => B1_IN4B, A5 => B1_IN6B, A4 => B1_IN11, 
	A3 => B1_IN12, A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15B);
GLB_B1_P7 : PGAND7
	PORT MAP (Z0 => B1_P7, A6 => B1_IN4, A5 => B1_IN6B, A4 => B1_IN11B, 
	A3 => B1_IN12B, A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15);
GLB_B1_P6 : PGAND7
	PORT MAP (Z0 => B1_P6, A6 => B1_IN4, A5 => B1_IN6, A4 => B1_IN11, 
	A3 => B1_IN12, A2 => B1_IN13, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P5 : PGAND7
	PORT MAP (Z0 => B1_P5, A6 => B1_IN4B, A5 => B1_IN6B, A4 => B1_IN11B, 
	A3 => B1_IN12, A2 => B1_IN13, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P4 : PGAND7
	PORT MAP (Z0 => B1_P4, A6 => B1_IN4, A5 => B1_IN6, A4 => B1_IN11, 
	A3 => B1_IN12B, A2 => B1_IN13B, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P3 : PGAND6
	PORT MAP (Z0 => B1_P3, A5 => B1_IN4B, A4 => B1_IN6, A3 => B1_IN12B, 
	A2 => B1_IN13, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P2 : PGAND6
	PORT MAP (Z0 => B1_P2, A5 => B1_IN4, A4 => B1_IN6B, A3 => B1_IN12, 
	A2 => B1_IN13B, A1 => B1_IN14, A0 => B1_IN15B);
GLB_B1_P1 : PGAND6
	PORT MAP (Z0 => B1_P1, A5 => B1_IN4, A4 => B1_IN6B, A3 => B1_IN12B, 
	A2 => B1_IN13, A1 => B1_IN14B, A0 => B1_IN15B);
GLB_B1_P0 : PGAND7
	PORT MAP (Z0 => B1_P0, A6 => B1_IN4B, A5 => B1_IN6, A4 => B1_IN11B, 
	A3 => B1_IN12, A2 => B1_IN13B, A1 => B1_IN14B, A0 => B1_IN15);
GLB_B1_G3 : PGORF73
	PORT MAP (Z0 => B1_G3, A2 => B1_F0, A1 => B1_F1, A0 => B1_F4);
GLB_B1_G1 : PGBUFI
	PORT MAP (Z0 => B1_G1, A0 => B1_F5);
GLB_B1_F5 : PGORF75
	PORT MAP (Z0 => B1_F5, A4 => B1_P13, A3 => B1_P14, A2 => B1_P15, 
	A1 => B1_P16, A0 => B1_P17);
GLB_B1_F4 : PGORF75
	PORT MAP (Z0 => B1_F4, A4 => B1_P8, A3 => B1_P9, A2 => B1_P10, 
	A1 => B1_P11, A0 => B1_P12);
GLB_B1_F1 : PGORF74
	PORT MAP (Z0 => B1_F1, A3 => B1_P4, A2 => B1_P5, A1 => B1_P6, 
	A0 => B1_P7);
GLB_B1_F0 : PGORF74
	PORT MAP (Z0 => B1_F0, A3 => B1_P0, A2 => B1_P1, A1 => B1_P2, 
	A0 => B1_P3);
GLB_QX_PIN : PGBUFI
	PORT MAP (Z0 => QX_PIN, A0 => B1_X2O);
GLB_FZ_PIN : PGBUFI
	PORT MAP (Z0 => FZ_PIN, A0 => B1_X0O);
GLB_B1_IN11 : PGBUFI
	PORT MAP (Z0 => B1_IN11, A0 => N_14_grp);
GLB_B1_IN14 : PGBUFI
	PORT MAP (Z0 => B1_IN14, A0 => N_16_grp);
GLB_B1_IN13 : PGBUFI
	PORT MAP (Z0 => B1_IN13, A0 => N_15_grp);
GLB_B1_IN4 : PGBUFI
	PORT MAP (Z0 => B1_IN4, A0 => N_12_grp);
GLB_B1_IN15 : PGBUFI
	PORT MAP (Z0 => B1_IN15, A0 => N_17_grp);
GLB_B1_IN12 : PGBUFI
	PORT MAP (Z0 => B1_IN12, A0 => N_11_grp);
GLB_B1_IN6 : PGBUFI
	PORT MAP (Z0 => B1_IN6, A0 => N_13_grp);
GLB_B1_X2O : PGXOR2
	PORT MAP (Z0 => B1_X2O, A1 => GND, A0 => B1_G1);
GLB_B1_X0O : PGXOR2
	PORT MAP (Z0 => B1_X0O, A1 => GND, A0 => B1_G3);
GLB_B1_IN15B : PGINVI
	PORT MAP (ZN0 => B1_IN15B, A0 => N_17_grp);
GLB_B1_IN12B : PGINVI
	PORT MAP (ZN0 => B1_IN12B, A0 => N_11_grp);
GLB_B1_IN6B : PGINVI
	PORT MAP (ZN0 => B1_IN6B, A0 => N_13_grp);
GLB_B1_IN14B : PGINVI
	PORT MAP (ZN0 => B1_IN14B, A0 => N_16_grp);
GLB_B1_IN13B : PGINVI
	PORT MAP (ZN0 => B1_IN13B, A0 => N_15_grp);
GLB_B1_IN11B : PGINVI
	PORT MAP (ZN0 => B1_IN11B, A0 => N_14_grp);
GLB_B1_IN4B : PGINVI
	PORT MAP (ZN0 => B1_IN4B, A0 => N_12_grp);
GLB_B3_P19 : PGAND8
	PORT MAP (Z0 => B3_P19, A7 => B3_IN4, A6 => B3_IN6B, A5 => B3_IN9, 
	A4 => B3_IN11B, A3 => B3_IN12, A2 => B3_IN13, A1 => B3_IN14B, 
	A0 => B3_IN15B);
GLB_B3_P18 : PGAND7
	PORT MAP (Z0 => B3_P18, A6 => B3_IN4B, A5 => B3_IN6, A4 => B3_IN9B, 
	A3 => B3_IN11B, A2 => B3_IN13, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P17 : PGAND7
	PORT MAP (Z0 => B3_P17, A6 => B3_IN4B, A5 => B3_IN6, A4 => B3_IN9, 
	A3 => B3_IN11B, A2 => B3_IN12B, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P16 : PGAND6
	PORT MAP (Z0 => B3_P16, A5 => B3_IN6, A4 => B3_IN11B, A3 => B3_IN12, 
	A2 => B3_IN13B, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P15 : PGAND7
	PORT MAP (Z0 => B3_P15, A6 => B3_IN4, A5 => B3_IN6, A4 => B3_IN9, 
	A3 => B3_IN12, A2 => B3_IN13B, A1 => B3_IN14B, A0 => B3_IN15);
GLB_B3_P14 : PGAND7
	PORT MAP (Z0 => B3_P14, A6 => B3_IN4, A5 => B3_IN6, A4 => B3_IN9, 
	A3 => B3_IN11B, A2 => B3_IN13B, A1 => B3_IN14B, A0 => B3_IN15);
GLB_B3_P13 : PGAND7
	PORT MAP (Z0 => B3_P13, A6 => B3_IN4, A5 => B3_IN6, A4 => B3_IN11B, 
	A3 => B3_IN12, A2 => B3_IN13B, A1 => B3_IN14B, A0 => B3_IN15);
GLB_B3_P12 : PGAND6
	PORT MAP (Z0 => B3_P12, A5 => B3_IN4B, A4 => B3_IN6B, A3 => B3_IN9B, 
	A2 => B3_IN11, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P11 : PGAND7
	PORT MAP (Z0 => B3_P11, A6 => B3_IN4, A5 => B3_IN6, A4 => B3_IN11B, 
	A3 => B3_IN12, A2 => B3_IN13B, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P10 : PGAND7
	PORT MAP (Z0 => B3_P10, A6 => B3_IN4B, A5 => B3_IN6B, A4 => B3_IN9B, 
	A3 => B3_IN11, A2 => B3_IN12B, A1 => B3_IN13, A0 => B3_IN15B);
GLB_B3_P9 : PGAND7
	PORT MAP (Z0 => B3_P9, A6 => B3_IN6B, A5 => B3_IN9B, A4 => B3_IN11, 
	A3 => B3_IN12B, A2 => B3_IN13, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P8 : PGAND7
	PORT MAP (Z0 => B3_P8, A6 => B3_IN6B, A5 => B3_IN9B, A4 => B3_IN11B, 
	A3 => B3_IN12B, A2 => B3_IN13B, A1 => B3_IN14B, A0 => B3_IN15B);
GLB_B3_P7 : PGAND4
	PORT MAP (Z0 => B3_P7, A3 => B3_IN11, A2 => B3_IN13B, A1 => B3_IN14B, 
	A0 => B3_IN15);
GLB_B3_P6 : PGAND5
	PORT MAP (Z0 => B3_P6, A4 => B3_IN4B, A3 => B3_IN6, A2 => B3_IN11B, 
	A1 => B3_IN13, A0 => B3_IN15B);
GLB_B3_P5 : PGAND5
	PORT MAP (Z0 => B3_P5, A4 => B3_IN4, A3 => B3_IN6, A2 => B3_IN11B, 
	A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P3 : PGAND6
	PORT MAP (Z0 => B3_P3, A5 => B3_IN4B, A4 => B3_IN6B, A3 => B3_IN11, 
	A2 => B3_IN12B, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P2 : PGAND6
	PORT MAP (Z0 => B3_P2, A5 => B3_IN4B, A4 => B3_IN6B, A3 => B3_IN11, 
	A2 => B3_IN13, A1 => B3_IN14, A0 => B3_IN15B);
GLB_B3_P1 : PGAND6
	PORT MAP (Z0 => B3_P1, A5 => B3_IN4, A4 => B3_IN6, A3 => B3_IN11B, 
	A2 => B3_IN13, A1 => B3_IN14B, A0 => B3_IN15B);
GLB_B3_P0 : PGAND6
	PORT MAP (Z0 => B3_P0, A5 => B3_IN4B, A4 => B3_IN6B, A3 => B3_IN11B, 
	A2 => B3_IN13B, A1 => B3_IN14B, A0 => B3_IN15B);
GLB_B3_G2 : PGORF72
	PORT MAP (Z0 => B3_G2, A1 => B3_F0, A0 => B3_F4);
GLB_B3_G1 : PGBUFI
	PORT MAP (Z0 => B3_G1, A0 => B3_F5);
GLB_B3_G0 : PGBUFI
	PORT MAP (Z0 => B3_G0, A0 => B3_F1);
GLB_B3_F5 : PGORF77
	PORT MAP (Z0 => B3_F5, A6 => B3_P13, A5 => B3_P14, A4 => B3_P15, 
	A3 => B3_P16, A2 => B3_P19, A1 => B3_P17, A0 => B3_P18);
GLB_B3_F4 : PGORF75
	PORT MAP (Z0 => B3_F4, A4 => B3_P8, A3 => B3_P9, A2 => B3_P10, 
	A1 => B3_P11, A0 => B3_P12);
GLB_B3_F1 : PGORF73
	PORT MAP (Z0 => B3_F1, A2 => B3_P5, A1 => B3_P6, A0 => B3_P7);
GLB_B3_F0 : PGORF74
	PORT MAP (Z0 => B3_F0, A3 => B3_P0, A2 => B3_P1, A1 => B3_P2, 
	A0 => B3_P3);
GLB_B3_X2MO : PGBUFI
	PORT MAP (Z0 => B3_X2MO, A0 => B3_G0);
GLB_CS_PIN : PGBUFI
	PORT MAP (Z0 => CS_PIN, A0 => B3_X2O);
GLB_JS_PIN : PGBUFI
	PORT MAP (Z0 => JS_PIN, A0 => B3_X1O);
GLB_B3_IN9 : PGBUFI
	PORT MAP (Z0 => B3_IN9, A0 => N_10_grp);
GLB_B3_IN12 : PGBUFI
	PORT MAP (Z0 => B3_IN12, A0 => N_11_grp);
GLB_B3_IN15 : PGBUFI
	PORT MAP (Z0 => B3_IN15, A0 => N_17_grp);
GLB_B3_IN14 : PGBUFI
	PORT MAP (Z0 => B3_IN14, A0 => N_16_grp);
GLB_B3_IN11 : PGBUFI
	PORT MAP (Z0 => B3_IN11, A0 => N_14_grp);
GLB_B3_IN13 : PGBUFI
	PORT MAP (Z0 => B3_IN13, A0 => N_15_grp);
GLB_B3_IN6 : PGBUFI
	PORT MAP (Z0 => B3_IN6, A0 => N_13_grp);
GLB_B3_IN4 : PGBUFI
	PORT MAP (Z0 => B3_IN4, A0 => N_12_grp);
GLB_B3_X2O : PGXOR2
	PORT MAP (Z0 => B3_X2O, A1 => B3_X2MO, A0 => B3_G1);
GLB_B3_X1O : PGXOR2
	PORT MAP (Z0 => B3_X1O, A1 => GND, A0 => B3_G2);
GLB_B3_IN9B : PGINVI
	PORT MAP (ZN0 => B3_IN9B, A0 => N_10_grp);
GLB_B3_IN12B : PGINVI
	PORT MAP (ZN0 => B3_IN12B, A0 => N_11_grp);
GLB_B3_IN15B : PGINVI
	PORT MAP (ZN0 => B3_IN15B, A0 => N_17_grp);
GLB_B3_IN14B : PGINVI
	PORT MAP (ZN0 => B3_IN14B, A0 => N_16_grp);
GLB_B3_IN13B : PGINVI
	PORT MAP (ZN0 => B3_IN13B, A0 => N_15_grp);
GLB_B3_IN11B : PGINVI
	PORT MAP (ZN0 => B3_IN11B, A0 => N_14_grp);
GLB_B3_IN6B : PGINVI
	PORT MAP (ZN0 => B3_IN6B, A0 => N_13_grp);
GLB_B3_IN4B : PGINVI
	PORT MAP (ZN0 => B3_IN4B, A0 => N_12_grp);
GLB_B6_P11 : PGAND3
	PORT MAP (Z0 => B6_P11, A2 => B6_IN13B, A1 => B6_IN14B, A0 => B6_IN15B);
GLB_B6_P10 : PGAND4
	PORT MAP (Z0 => B6_P10, A3 => B6_IN4B, A2 => B6_IN11B, A1 => B6_IN14B, 
	A0 => B6_IN15B);
GLB_B6_P9 : PGAND4
	PORT MAP (Z0 => B6_P9, A3 => B6_IN6B, A2 => B6_IN11B, A1 => B6_IN14B, 
	A0 => B6_IN15B);
GLB_B6_F2 : PGORF73
	PORT MAP (Z0 => B6_F2, A2 => B6_P9, A1 => B6_P10, A0 => B6_P11);
GLB_XI_PIN : PGBUFI
	PORT MAP (Z0 => XI_PIN, A0 => B6_F2);
GLB_B6_IN13B : PGINVI
	PORT MAP (ZN0 => B6_IN13B, A0 => N_15_grp);
GLB_B6_IN4B : PGINVI
	PORT MAP (ZN0 => B6_IN4B, A0 => N_12_grp);
GLB_B6_IN15B : PGINVI
	PORT MAP (ZN0 => B6_IN15B, A0 => N_17_grp);
GLB_B6_IN14B : PGINVI
	PORT MAP (ZN0 => B6_IN14B, A0 => N_16_grp);
GLB_B6_IN11B : PGINVI
	PORT MAP (ZN0 => B6_IN11B, A0 => N_14_grp);
GLB_B6_IN6B : PGINVI
	PORT MAP (ZN0 => B6_IN6B, A0 => N_13_grp);
IOC_L2L_KEYWD_RESET : PXIN
	PORT MAP (Z0 => L2L_KEYWD_RESETb, XI0 => XRESET);
IOC_IO24_IBUFO : PXIN
	PORT MAP (Z0 => IO24_IBUFO, XI0 => CP);
IOC_ZZ : PXOUT
	PORT MAP (XO0 => ZZ, A0 => IO27_OBUFI);
IOC_IO27_OBUFI : PGBUFI
	PORT MAP (Z0 => IO27_OBUFI, A0 => ZZ_PIN_iomux);
IOC_XI : PXOUT
	PORT MAP (XO0 => XI, A0 => IO29_OBUFI);
IOC_IO29_OBUFI : PGBUFI
	PORT MAP (Z0 => IO29_OBUFI, A0 => XI_PIN_iomux);
IOC_TS : PXOUT
	PORT MAP (XO0 => TS, A0 => IO1_OBUFI);
IOC_IO1_OBUFI : PGBUFI
	PORT MAP (Z0 => IO1_OBUFI, A0 => OR_777_iomux);
IOC_QX : PXOUT
	PORT MAP (XO0 => QX, A0 => IO30_OBUFI);
IOC_IO30_OBUFI : PGBUFI
	PORT MAP (Z0 => IO30_OBUFI, A0 => QX_PIN_iomux);
IOC_OK : PXOUT
	PORT MAP (XO0 => OK, A0 => IO0_OBUFI);
IOC_IO0_OBUFI : PGBUFI
	PORT MAP (Z0 => IO0_OBUFI, A0 => OK_PIN_iomux);
IOC_JS : PXOUT
	PORT MAP (XO0 => JS, A0 => IO25_OBUFI);
IOC_IO25_OBUFI : PGBUFI
	PORT MAP (Z0 => IO25_OBUFI, A0 => JS_PIN_iomux);
IOC_FZ : PXOUT
	PORT MAP (XO0 => FZ, A0 => IO28_OBUFI);
IOC_IO28_OBUFI : PGBUFI
	PORT MAP (Z0 => IO28_OBUFI, A0 => FZ_PIN_iomux);
IOC_CS : PXOUT
	PORT MAP (XO0 => CS, A0 => IO26_OBUFI);
IOC_IO26_OBUFI : PGBUFI
	PORT MAP (Z0 => IO26_OBUFI, A0 => CS_PIN_iomux);
GRP_N_13_ffb : PGBUFI
	PORT MAP (Z0 => N_13_ffb, A0 => N_13);
GRP_N_13_grp : PGBUFI
	PORT MAP (Z0 => N_13_grp, A0 => N_13);
GRP_N_12_ffb : PGBUFI
	PORT MAP (Z0 => N_12_ffb, A0 => N_12);
GRP_N_12_grp : PGBUFI
	PORT MAP (Z0 => N_12_grp, A0 => N_12);
GRP_N_10_ffb : PGBUFI
	PORT MAP (Z0 => N_10_ffb, A0 => N_10);
GRP_N_10_grp : PGBUFI
	PORT MAP (Z0 => N_10_grp, A0 => N_10);
GRP_N_11_ffb : PGBUFI
	PORT MAP (Z0 => N_11_ffb, A0 => N_11);
GRP_N_11_grp : PGBUFI
	PORT MAP (Z0 => N_11_grp, A0 => N_11);
GRP_N_15_ffb : PGBUFI
	PORT MAP (Z0 => N_15_ffb, A0 => N_15);
GRP_N_15_grp : PGBUFI
	PORT MAP (Z0 => N_15_grp, A0 => N_15);
GRP_N_16_grp : PGBUFI
	PORT MAP (Z0 => N_16_grp, A0 => N_16);
GRP_N_17_grp : PGBUFI
	PORT MAP (Z0 => N_17_grp, A0 => N_17);
GRP_BUF_1197_ck2f : PGBUFI
	PORT MAP (Z0 => BUF_1197_ck2f, A0 => BUF_1197);
GRP_N_14_grp : PGBUFI
	PORT MAP (Z0 => N_14_grp, A0 => N_14);
GRP_OR_777_iomux : PGBUFI
	PORT MAP (Z0 => OR_777_iomux, A0 => OR_777);
GRP_OR_1116_grp : PGBUFI
	PORT MAP (Z0 => OR_1116_grp, A0 => OR_1116);
GRP_OK_PIN_iomux : PGBUFI
	PORT MAP (Z0 => OK_PIN_iomux, A0 => OK_PIN);
GRP_ZZ_PIN_iomux : PGBUFI
	PORT MAP (Z0 => ZZ_PIN_iomux, A0 => ZZ_PIN);
GRP_CPX_grp : PGBUFI
	PORT MAP (Z0 => CPX_grp, A0 => IO24_IBUFO);
GRP_QX_PIN_iomux : PGBUFI
	PORT MAP (Z0 => QX_PIN_iomux, A0 => QX_PIN);
GRP_FZ_PIN_iomux : PGBUFI
	PORT MAP (Z0 => FZ_PIN_iomux, A0 => FZ_PIN);
GRP_JS_PIN_iomux : PGBUFI
	PORT MAP (Z0 => JS_PIN_iomux, A0 => JS_PIN);
GRP_CS_PIN_iomux : PGBUFI
	PORT MAP (Z0 => CS_PIN_iomux, A0 => CS_PIN);
GRP_XI_PIN_iomux : PGBUFI
	PORT MAP (Z0 => XI_PIN_iomux, A0 => XI_PIN);
GRP_L2L_KEYWD_RESET_glb : PXIN
	PORT MAP (Z0 => L2L_KEYWD_RESET_glbb, XI0 => L2L_KEYWD_RESETb);
END yuanli_STRUCTURE;