wash.vto

洗衣机的程序 洗衣机的程序

-- VHDL netlist for yuanli
-- Date: Sat Apr 19 19:02:18 2008
-- Copyright (c) Lattice Semiconductor Corporation
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
LIBRARY LAT_VITL; -- Lattice Vital library 
USE LAT_VITL.vit_pkg.all;
USE work.all;

ENTITY yuanli IS 
    PORT (
        XRESET : IN std_logic;
        CP : IN std_logic;
        ZZ : OUT std_logic;
        XI : OUT std_logic;
        TS : OUT std_logic;
        QX : OUT std_logic;
        OK : OUT std_logic;
        JS : OUT std_logic;
        FZ : OUT std_logic;
        CS : OUT std_logic
    );
END yuanli;


ARCHITECTURE yuanli_STRUCTURE OF yuanli IS
SIGNAL VCC : std_logic := '1';
SIGNAL GND : std_logic := '0';
SIGNAL  BUF_1197_ck2f, L2L_KEYWD_RESETb, IO24_IBUFO, IO27_OBUFI,
	 ZZ_PIN_iomux, IO29_OBUFI, XI_PIN_iomux, IO1_OBUFI,
	 OR_777_iomux, IO30_OBUFI, QX_PIN_iomux, IO0_OBUFI,
	 OK_PIN_iomux, IO25_OBUFI, JS_PIN_iomux, IO28_OBUFI,
	 FZ_PIN_iomux, IO26_OBUFI, CS_PIN_iomux, N_12,
	 N_13, N_12_D0, N_13_D0, A2_CLK,
	 A2_P0_xa, A2_G2, A2_G0, A2_F5,
	 A2_F4, A2_P18, A2_IN16, A2_P17,
	 A2_P16, A2_P15, N_13_ffb, A2_P14,
	 A2_IN16B, A2_P13, A2_P12, A2_IN6B,
	 A2_P11, A2_IN3B, A2_IN17B, A2_P10,
	 A2_IN2, A2_P9, A2_IN0, A2_IN1,
	 N_12_ffb, A2_P8, A2_IN3, A2_IN6,
	 A2_IN17, A2_P0, N_11, N_15,
	 N_16, N_17, N_11_D0, N_15_D0,
	 N_16_D0, N_17_D0, A4_CLK, A4_P0_xa,
	 A4_P4_xa, A4_P8_xa, A4_P13_xa, A4_G3,
	 A4_G2, A4_G1, A4_G0, A4_F5,
	 A4_F4, A4_F1, A4_F0, A4_P18,
	 A4_P17, A4_P16, A4_P15, A4_IN6B,
	 A4_IN17B, A4_P14, A4_P13, A4_P12,
	 A4_P8, A4_P7, A4_P4, A4_P3,
	 A4_IN0, A4_IN1B, A4_IN16B, N_11_ffb,
	 N_15_ffb, A4_P2, A4_IN0B, A4_IN1,
	 A4_IN4, A4_IN6, A4_IN9, A4_IN11,
	 A4_IN16, A4_IN17, A4_P0, N_10,
	 N_14, L2L_KEYWD_RESET_glbb, N_10_D0, N_14_D0,
	 A5_CLK, A5_P4_xa, A5_G3, A5_G1,
	 A5_F5, A5_F0, A5_P19, A5_P18,
	 A5_P17, A5_P16, A5_IN16B, A5_P15,
	 A5_IN3B, A5_P14, A5_IN11B, A5_P13,
	 A5_IN4B, A5_IN9B, A5_P4, N_10_ffb,
	 A5_P3, A5_IN16, A5_P2, A5_IN2,
	 A5_P1, A5_IN1, A5_P0, A5_IN0,
	 A5_IN3, A5_IN4, A5_IN9, A5_IN11,
	 OR_1116, A6_X2O, OR_777, A6_X1O,
	 OK_PIN, A6_X0O, A6_G3, A6_G2,
	 A6_G1, A6_F5, A6_F4, A6_F1,
	 A6_F0, A6_P19, A6_P18, A6_P17,
	 A6_P16, A6_P15, A6_P14, A6_P13,
	 A6_IN4B, A6_P12, A6_P11, A6_P7,
	 A6_P6, A6_IN9, A6_IN11B, A6_P5,
	 A6_P3, A6_IN0, A6_IN1B, A6_IN4,
	 A6_P2, A6_IN3, A6_P1, A6_IN2,
	 A6_IN6, A6_P0, A6_IN0B, A6_IN1,
	 A6_IN2B, A6_IN3B, A6_IN6B, A6_IN9B,
	 A6_IN11, B0_X3MO, ZZ_PIN, B0_X3O,
	 B0_P8_xa, BUF_1197, B0_X1O, B0_G3,
	 B0_G2, B0_G0, B0_F5, B0_F4,
	 B0_F1, B0_F0, B0_P19, B0_P18,
	 B0_P17, B0_P16, B0_P15, B0_P14,
	 B0_IN5, B0_P12, B0_P11, CPX_grp,
	 B0_P8, B0_IN7, B0_P7, B0_P6,
	 B0_P5, OR_1116_grp, B0_P4, B0_IN5B,
	 B0_IN11B, B0_P3, B0_P2, B0_IN4,
	 B0_IN11, B0_IN13, B0_P1, B0_IN6,
	 B0_IN9B, B0_IN12B, B0_IN14B, B0_IN15,
	 B0_P0, B0_IN4B, B0_IN6B, B0_IN9,
	 B0_IN12, B0_IN13B, B0_IN14, B0_IN15B,
	 QX_PIN, B1_X2O, FZ_PIN, B1_X0O,
	 B1_G3, B1_G1, B1_F5, B1_F4,
	 B1_F1, B1_F0, B1_P17, B1_P16,
	 B1_P15, B1_P14, B1_P13, B1_P12,
	 B1_P11, B1_P10, B1_P9, B1_P8,
	 B1_P7, B1_P6, B1_P5, B1_P4,
	 B1_IN11, B1_P3, B1_P2, B1_IN14,
	 B1_P1, B1_IN4, B1_IN6B, B1_IN12B,
	 B1_IN13, B1_IN15B, B1_P0, B1_IN4B,
	 B1_IN6, B1_IN11B, B1_IN12, B1_IN13B,
	 B1_IN14B, B1_IN15, B3_X2MO, CS_PIN,
	 B3_X2O, JS_PIN, B3_X1O, B3_G2,
	 B3_G1, B3_G0, B3_F5, B3_F4,
	 B3_F1, B3_F0, B3_P19, B3_P18,
	 B3_P17, B3_P16, B3_P15, B3_P14,
	 B3_IN9, B3_P13, B3_P12, B3_P11,
	 B3_IN12, B3_P10, B3_P9, N_10_grp,
	 B3_P8, B3_IN9B, B3_P7, B3_IN15,
	 B3_P6, B3_P5, N_11_grp, B3_P3,
	 B3_IN12B, B3_P2, B3_IN11, B3_IN14,
	 B3_P1, B3_IN4, B3_IN6, B3_IN13,
	 B3_P0, B3_IN4B, B3_IN6B, B3_IN11B,
	 B3_IN13B, B3_IN14B, B3_IN15B, XI_PIN,
	 B6_F2, N_15_grp, B6_P11, B6_IN13B,
	 N_12_grp, B6_P10, B6_IN4B, N_17_grp,
	 N_16_grp, N_14_grp, N_13_grp, B6_P9,
	 B6_IN6B, B6_IN11B, B6_IN14B, B6_IN15B : std_logic;


  COMPONENT PGAND4
    PORT (
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND4 use entity lat_vitl.PGAND4(behav);

  COMPONENT PGAND2
    PORT (
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND2 use entity lat_vitl.PGAND2(behav);

  COMPONENT PGAND3
    PORT (
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND3 use entity lat_vitl.PGAND3(behav);

  COMPONENT PGBUFI
    PORT (
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGBUFI use entity lat_vitl.PGBUFI(behav);

  COMPONENT PGORF76
    PORT (
        A5 : IN std_logic;
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF76 use entity lat_vitl.PGORF76(behav);

  COMPONENT PGORF75
    PORT (
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF75 use entity lat_vitl.PGORF75(behav);

  COMPONENT PGXOR2
    PORT (
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGXOR2 use entity lat_vitl.PGXOR2(behav);

  COMPONENT PGDFFR
    PORT (
        RNESET : IN std_logic;
        CD : IN std_logic;
        CLK : IN std_logic;
        D0 : IN std_logic;
        Q0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGDFFR use entity lat_vitl.PGDFFR(behav);

  COMPONENT PGINVI
    PORT (
        A0 : IN std_logic;
        ZN0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGINVI use entity lat_vitl.PGINVI(behav);

  COMPONENT PGAND5
    PORT (
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND5 use entity lat_vitl.PGAND5(behav);

  COMPONENT PGAND6
    PORT (
        A5 : IN std_logic;
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND6 use entity lat_vitl.PGAND6(behav);

  COMPONENT PGAND7
    PORT (
        A6 : IN std_logic;
        A5 : IN std_logic;
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND7 use entity lat_vitl.PGAND7(behav);

  COMPONENT PGAND8
    PORT (
        A7 : IN std_logic;
        A6 : IN std_logic;
        A5 : IN std_logic;
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGAND8 use entity lat_vitl.PGAND8(behav);

  COMPONENT PGORF72
    PORT (
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF72 use entity lat_vitl.PGORF72(behav);

  COMPONENT PGORF77
    PORT (
        A6 : IN std_logic;
        A5 : IN std_logic;
        A4 : IN std_logic;
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF77 use entity lat_vitl.PGORF77(behav);

  COMPONENT PGORF74
    PORT (
        A3 : IN std_logic;
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF74 use entity lat_vitl.PGORF74(behav);

  COMPONENT PGORF73
    PORT (
        A2 : IN std_logic;
        A1 : IN std_logic;
        A0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PGORF73 use entity lat_vitl.PGORF73(behav);

  COMPONENT PXIN
    PORT (
        XI0 : IN std_logic;
        Z0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PXIN use entity lat_vitl.PXIN(behav);

  COMPONENT PXOUT
    PORT (
        A0 : IN std_logic;
        XO0 : OUT std_logic
    );
  END COMPONENT;
  for all :  PXOUT use entity lat_vitl.PXOUT(behav);

BEGIN

GLB_A2_P18 : PGAND4
	PORT MAP (Z0 => A2_P18, A3 => A2_IN3, A2 => A2_IN6, A1 => A2_IN16, 
	A0 => A2_IN17);
GLB_A2_P17 : PGAND2
	PORT MAP (Z0 => A2_P17, A1 => A2_IN0, A0 => A2_IN1);
GLB_A2_P16 : PGAND2
	PORT MAP (Z0 => A2_P16, A1 => A2_IN6B, A0 => A2_IN16B);
GLB_A2_P15 : PGAND2
	PORT MAP (Z0 => A2_P15, A1 => A2_IN3B, A0 => A2_IN16B);
GLB_A2_P14 : PGAND2
	PORT MAP (Z0 => A2_P14, A1 => A2_IN16B, A0 => A2_IN17B);
GLB_A2_P13 : PGAND2
	PORT MAP (Z0 => A2_P13, A1 => A2_IN0, A0 => A2_IN2);
GLB_A2_P12 : PGAND2
	PORT MAP (Z0 => A2_P12, A1 => A2_IN6B, A0 => A2_IN17B);
GLB_A2_P11 : PGAND2
	PORT MAP (Z0 => A2_P11, A1 => A2_IN3B, A0 => A2_IN17B);
GLB_A2_P10 : PGAND2
	PORT MAP (Z0 => A2_P10, A1 => A2_IN0, A0 => A2_IN2);
GLB_A2_P9 : PGAND2
	PORT MAP (Z0 => A2_P9, A1 => A2_IN0, A0 => A2_IN1);
GLB_A2_P8 : PGAND3
	PORT MAP (Z0 => A2_P8, A2 => A2_IN3, A1 => A2_IN6, A0 => A2_IN17);
GLB_A2_P0 : PGBUFI
	PORT MAP (Z0 => A2_P0, A0 => VCC);
GLB_A2_G2 : PGBUFI
	PORT MAP (Z0 => A2_G2, A0 => A2_F5);
GLB_A2_G0 : PGBUFI
	PORT MAP (Z0 => A2_G0, A0 => A2_F4);
GLB_A2_F5 : PGORF76
	PORT MAP (Z0 => A2_F5, A5 => A2_P13, A4 => A2_P14, A3 => A2_P15, 
	A2 => A2_P16, A1 => A2_P17, A0 => A2_P18);
GLB_A2_F4 : PGORF75
	PORT MAP (Z0 => A2_F4, A4 => A2_P8, A3 => A2_P9, A2 => A2_P10, 
	A1 => A2_P11, A0 => A2_P12);
GLB_A2_CLK : PGBUFI
	PORT MAP (Z0 => A2_CLK, A0 => BUF_1197_ck2f);
GLB_A2_P0_xa : PGBUFI
	PORT MAP (Z0 => A2_P0_xa, A0 => A2_P0);
GLB_A2_IN16 : PGBUFI
	PORT MAP (Z0 => A2_IN16, A0 => N_13_ffb);
GLB_A2_IN2 : PGBUFI
	PORT MAP (Z0 => A2_IN2, A0 => N_15_grp);
GLB_A2_IN1 : PGBUFI
	PORT MAP (Z0 => A2_IN1, A0 => N_16_grp);
GLB_A2_IN0 : PGBUFI
	PORT MAP (Z0 => A2_IN0, A0 => N_17_grp);
GLB_A2_IN17 : PGBUFI
	PORT MAP (Z0 => A2_IN17, A0 => N_12_ffb);
GLB_A2_IN6 : PGBUFI
	PORT MAP (Z0 => A2_IN6, A0 => N_10_grp);
GLB_A2_IN3 : PGBUFI
	PORT MAP (Z0 => A2_IN3, A0 => N_11_grp);
GLB_N_12_D0 : PGXOR2
	PORT MAP (Z0 => N_12_D0, A1 => A2_P0_xa, A0 => A2_G0);
GLB_N_13_D0 : PGXOR2
	PORT MAP (Z0 => N_13_D0, A1 => VCC, A0 => A2_G2);
GLB_N_12 : PGDFFR
	PORT MAP (Q0 => N_12, RNESET => L2L_KEYWD_RESET_glbb, CD => GND, CLK => A2_CLK,