wash.lct

洗衣机的程序 洗衣机的程序

[Device]
Family = plsi1k;
PartNumber = ispLSI1016-60LH44/883;
Package = 44JLCC;
PartType = ispLSI1016;
Speed = 60;
Operating_condition = MIL;
Status = Production;

[Revision]
Parent = lc1k.lci;
DATE = 2002;
TIME = 0:00:00;
Source_Format = ABEL_Schematic;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;
OK = pin, 15, -, -;
TS = pin, 16, -, -;
QX = pin, 9, -, -;
XI = pin, 8, -, -;
FZ = pin, 7, -, -;
ZZ = pin, 6, -, -;
CS = pin, 5, -, -;
JS = pin, 4, -, -;
CP = pin, 3, -, -;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]

[opt global constraints list]

[Explorer User Settings]

[Pin attributes list]

[global constraints list]

[Global Constraints Process Update]

[pin lock limitation]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[individual constraints list]

[Attributes list setting]

[Timing Analyzer]

[PLL Assignments]

[Dual Function Macrocell]

[Explorer Results]

[VHDL synplify constraints]

[VHDL spectrum constraints]

[verilog synplify constraints]

[verilog spectrum constraints]

[VHDL synplify constraints list]

[VHDL spectrum constraints list]

[verilog synplify constraints list]

[verilog spectrum constraints list]

[symbol/module attribute]
layer = OFF;

[symbol/module attribute list]

[Node attribute list]