📄 wash.rpt
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8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
6 Fanout(s)
glb06.I6, glb05.I6, glb03_part2.I16, glb04.I6, glb00.I9,
glb01.I9
5 Product Term(s)
1 GLB Level(s)
N_10.D = (N_10
# N_15 & N_17
# N_16 & N_17
# N_11 & N_12 & N_13 & N_14 & N_17)
$ VCC
N_10.C = BUF_1197
N_10.R =
GLB glb04, A6
8 Input(s)
(glb03_part2.O2, N_10, I6), (glb05.O3, N_11, I3), (glb06.O3,
N_12, I11), (glb06.O1, N_13, I9), (glb03_part2.O0, N_14, I4),
(glb05.O2, N_15, I2), (glb05.O1, N_16, I1), (glb05.O0,
N_17, I0)
3 Output(s)
(OR_777, O1), (OR_1116, O2), (OK_PIN, O0)
16 Product Term(s)
Output OR_777
7 Input(s)
N_17, N_11, N_12, N_13, N_14, N_15, N_16
1 Fanout(s)
TS.IR
3 Product Term(s)
1 GLB Level(s)
OR_777 = (N_11 & N_14 & N_17 & !N_15 & !N_16 & !N_12
# N_13 & N_14 & N_17 & !N_15 & !N_16 & !N_12
# N_12 & N_14 & N_17 & !N_15 & !N_16 & !N_13)
Output OR_1116
8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
1 Fanout(s)
glb00.I5
11 Product Term(s)
1 GLB Level(s)
OR_1116 = (N_12 & N_14 & N_17 & !N_15 & !N_16 & !N_10
# N_11 & N_12 & N_15 & N_16 & !N_17 & !N_10 & !N_13
# N_10 & N_12 & N_15 & N_16 & !N_17 & !N_11 & !N_13
# N_12 & N_16 & !N_17 & !N_15 & !N_10 & !N_11 & !N_13
# N_12 & N_13 & N_14 & N_15 & N_16 & !N_17 & !N_10 & !N_11
# N_15 & N_16 & !N_17 & !N_14 & !N_10 & !N_11 & !N_12 & !N_13
# N_10 & N_11 & N_12 & N_13 & N_14 & N_16 & !N_17 & !N_15
# N_11 & N_13 & N_14 & N_16 & !N_17 & !N_15 & !N_10 & !N_12
# N_11 & N_12 & N_13 & N_14 & N_15 & !N_17 & !N_16 & !N_10
# N_14 & !N_17 & !N_15 & !N_16 & !N_10 & !N_11 & !N_12
& !N_13
# N_10 & N_11 & N_12 & N_13 & !N_17 & !N_15 & !N_16 & !N_14
)
Output OK_PIN
8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
1 Fanout(s)
OK.IR
2 Product Term(s)
1 GLB Level(s)
OK_PIN = (N_12 & N_13 & N_14 & N_17 & !N_15 & !N_16 & !N_10
# N_12 & N_13 & N_14 & N_17 & !N_15 & !N_16 & !N_11)
GLB glb05, A4
8 Input(s)
(glb03_part2.O2, N_10, I6), (glb05.O3, N_11, I17), (glb06.O3,
N_12, I11), (glb06.O1, N_13, I9), (glb03_part2.O0, N_14, I4),
(glb05.O2, N_15, I16), (glb05.O1, N_16, I1), (glb05.O0,
N_17, I0)
4 Output(s)
(N_17, O0), (N_16, O1), (N_15, O2), (N_11, O3)
12 Product Term(s)
Output N_17
8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
8 Fanout(s)
glb06.I0, glb05.I0, glb03_part2.I0, glb04.I0, glb00.I15,
glb02.I15, glb01.I15, glb03_part1.I15
3 Product Term(s)
1 GLB Level(s)
N_17.D = (N_10 & N_11 & N_12 & N_13 & N_14 & N_17 & !N_15 & !N_16
# N_10 & N_11 & N_12 & N_13 & N_14 & N_15 & N_16 & !N_17)
$ N_17 & !N_15 & !N_16
N_17.C = BUF_1197
N_17.R =
Output N_16
8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
8 Fanout(s)
glb06.I1, glb05.I1, glb03_part2.I1, glb04.I1, glb00.I14,
glb02.I14, glb01.I14, glb03_part1.I14
2 Product Term(s)
1 GLB Level(s)
N_16.D = (N_10 & N_11 & N_12 & N_13 & N_14 & N_15 & !N_17)
$ N_16 & !N_17
N_16.C = BUF_1197
N_16.R =
Output N_15
7 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15
8 Fanout(s)
glb06.I2, glb05.I16, glb03_part2.I2, glb04.I2, glb00.I13,
glb02.I13, glb01.I13, glb03_part1.I13
2 Product Term(s)
1 GLB Level(s)
N_15.D = (N_10 & N_11 & N_12 & N_13 & N_14 & !N_17)
$ N_15 & !N_17
N_15.C = BUF_1197
N_15.R =
Output N_11
8 Input(s)
N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
7 Fanout(s)
glb06.I3, glb05.I17, glb03_part2.I3, glb04.I3, glb00.I12,
glb02.I12, glb01.I12
6 Product Term(s)
1 GLB Level(s)
N_11.D = (N_10 & N_11
# !N_10 & !N_11
# N_15 & N_17
# N_16 & N_17
# N_12 & N_13 & N_14 & N_17 & !N_10)
$ VCC
N_11.C = BUF_1197
N_11.R =
GLB glb06, A2
7 Input(s)
(glb03_part2.O2, N_10, I6), (glb05.O3, N_11, I3), (glb06.O3,
N_12, I17), (glb06.O1, N_13, I16), (glb05.O2, N_15, I2),
(glb05.O1, N_16, I1), (glb05.O0, N_17, I0)
2 Output(s)
(N_13, O1), (N_12, O3)
11 Product Term(s)
Output N_13
7 Input(s)
N_17, N_10, N_11, N_12, N_13, N_15, N_16
8 Fanout(s)
glb06.I16, glb05.I9, glb03_part2.I9, glb04.I9, glb00.I6,
glb02.I6, glb01.I6, glb03_part1.I6
7 Product Term(s)
1 GLB Level(s)
N_13.D = (!N_10 & !N_13
# !N_11 & !N_13
# !N_12 & !N_13
# N_15 & N_17
# N_16 & N_17
# N_10 & N_11 & N_12 & N_13)
$ VCC
N_13.C = BUF_1197
N_13.R =
Output N_12
6 Input(s)
N_17, N_10, N_11, N_12, N_15, N_16
8 Fanout(s)
glb06.I17, glb05.I11, glb03_part2.I11, glb04.I11, glb00.I4,
glb02.I4, glb01.I4, glb03_part1.I4
6 Product Term(s)
1 GLB Level(s)
N_12.D = (!N_10 & !N_12
# !N_11 & !N_12
# N_15 & N_17
# N_16 & N_17
# N_10 & N_11 & N_12)
$ VCC
N_12.C = BUF_1197
N_12.R =
Input CP, IO24
Output CPX
1 Fanout(s)
glb00.I7
Output CS, IO26
Input (glb01.O2, CS_PIN)
CS = CS_PIN
Output FZ, IO28
Input (glb02.O0, FZ_PIN)
FZ = FZ_PIN
Output JS, IO25
Input (glb01.O1, JS_PIN)
JS = JS_PIN
Output OK, IO0
Input (glb04.O0, OK_PIN)
OK = OK_PIN
Output QX, IO30
Input (glb02.O2, QX_PIN)
QX = QX_PIN
Output TS, IO1
Input (glb04.O1, OR_777)
TS = OR_777
Output XI, IO29
Input (glb03_part1.O1, XI_PIN)
XI = XI_PIN
Output ZZ, IO27
Input (glb00.O3, ZZ_PIN)
ZZ = ZZ_PIN
Clock Assignments
Net Name Clock Assignment
BUF_1197 Internal CLK2
GLB and GLB Output Statistics
GLB Name, Location GLB Statistics GLB Output Statistics
GLB Output Name Ins, Outs, PTs Ins, FOs, PTs, Levels, PTSABP
glb00, B0 10, 2, 17
BUF_1197 1, 3, 1, 1, 1PT
ZZ_PIN 9, 1, 16, 2, -
glb01, B3 8, 2, 19
CS_PIN 8, 1, 10, 1, -
JS_PIN 8, 1, 9, 1, -
glb02, B1 7, 2, 18
FZ_PIN 7, 1, 13, 1, -
QX_PIN 7, 1, 5, 1, -
glb03_part1, B6 6, 1, 5
XI_PIN 6, 1, 3, 1, 4PT
glb03_part2, A5 8, 2, 11
N_10 8, 6, 5, 1, -
N_14 8, 7, 8, 1, -
glb04, A6 8, 3, 16
OK_PIN 8, 1, 2, 1, -
OR_1116 8, 1, 11, 1, -
OR_777 7, 1, 3, 1, -
glb05, A4 8, 4, 12
N_11 8, 7, 6, 1, -
N_15 7, 8, 2, 1, -
N_16 8, 8, 2, 1, -
N_17 8, 8, 3, 1, -
glb06, A2 7, 2, 11
N_12 6, 8, 6, 1, -
N_13 7, 8, 7, 1, -
Maximum-Level Trace
GLB Level, Name, Ins GLB Output Name
2, glb00, 8 ZZ_PIN
1, glb04 OR_1116
Pin Assignments
Pin Name Pin Assignment Pin Type, Pin Attribute
CP 3 Input, PULLUP
JS 4 Output, PULLUP
CS 5 Output, PULLUP
ZZ 6 Output, PULLUP
FZ 7 Output, PULLUP
XI 8 Output, PULLUP
QX 9 Output, PULLUP
OK 15 Output, PULLUP
TS 16 Output, PULLUP
Design process management completed successfully
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