wash.rpt

洗衣机的程序 洗衣机的程序

ispEXPERT Compiler Release 6.1.00.37.42.06, May 20 2002 13:06:40


Design Parameters
-----------------

EFFORT:                         MEDIUM (2)
IGNORE_FIXED_PIN:               OFF
MAX_GLB_IN:                     16
MAX_GLB_OUT:                    4
OUTPUT_FORM:                    VERILOG, VHDL
OS_VERSION:                     Windows NT 5.1
PARAM_FILE:                     'e:\wash\ispxpert'
PIN_FILE:                       'e:\wash\WASH.xpn'
STRATEGY:                       DELAY
TIMING_ANALYZER:                ON 
USE_GLOBAL_RESET:               ON


Design Specification
--------------------

Design:                         wash
Part:                           ispLSI1016-60LH44/883


ISP:                            ON
ISP_EXCEPT_Y2:                  OFF
PULL:                           UP
SECURITY:                       OFF
Y1_AS_RESET:                    ON


Number of Critical Pins:        0
Number of Free Pins:            0
Number of Locked Pins:          9
Number of Reserved Pins:        0


Input Pins

    Pin Name                Pin Attribute

        CP                      LOCK 3, PULLUP


Output Pins

    Pin Name                Pin Attribute

        CS                      LOCK 5, PULLUP
        FZ                      LOCK 7, PULLUP
        JS                      LOCK 4, PULLUP
        OK                      LOCK 15, PULLUP
        QX                      LOCK 9, PULLUP
        TS                      LOCK 16, PULLUP
        XI                      LOCK 8, PULLUP
        ZZ                      LOCK 6, PULLUP


Pre-Route Design Statistics
---------------------------

Number of Macrocells:           18
Number of GLBs:                 7
Number of I/Os:                 9
Number of Nets:                 18

Number of Free Inputs:          0
Number of Free Outputs:         0
Number of Free Three-States:    0
Number of Free Bidi's:          0

Number of Locked Input IOCs:    1
Number of Locked DIs:           0
Number of Locked Outputs:       8
Number of Locked Three-States:  0
Number of Locked Bidi's:        0

Number of CRIT Outputs:         0
Number of Global OEs:           0
Number of External Clocks:      0


GLB Utilization (Out of 16):	43%
I/O Utilization (Out of 33):	27%
Net Utilization (Out of 97):	18%


Nets with Fanout of  1:         10
Nets with Fanout of  6:         2
Nets with Fanout of  7:         6

Average Fanout per Net:         3.56


GLBs with  7 Input(s):          2
GLBs with  8 Input(s):          4
GLBs with 10 Input(s):          1

Average Inputs per GLB:         8.00


GLBs with  2 Output(s):         4
GLBs with  3 Output(s):         2
GLBs with  4 Output(s):         1

Average Outputs per GLB:        2.57


Number of GLB Registers:        8
Number of IOC Registers:        0


Post-Route Design Implementation
--------------------------------

Number of Macrocells:		18
Number of GLBs:			8
Number of IOCs:			9
Number of DIs:			0
Number of GLB Levels:		2


Clock GLB glb00, B0

    10 Input(s)
        (CP.O, CPX, I7), (glb03_part2.O2, N_10, I9), (glb05.O3, 
        N_11, I12), (glb06.O3, N_12, I4), (glb06.O1, N_13, I6), 
        (glb03_part2.O0, N_14, I11), (glb05.O2, N_15, I13), (glb05.O1, 
        N_16, I14), (glb05.O0, N_17, I15), (glb04.O2, OR_1116, I5)
    2 Output(s)
        (ZZ_PIN, O3), (BUF_1197, O1)
    17 Product Term(s)

    Output ZZ_PIN

        9 Input(s)
            N_17, N_10, OR_1116, N_11, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            ZZ.IR
        16 Product Term(s)
        2 GLB Level(s)

        ZZ_PIN = (N_13 & N_14 & N_17 & !N_15 & !N_16 & !N_12
            # N_10 & N_11 & N_12 & N_14 & N_15 & !N_17 & !N_16 & !N_13
            # N_13 & N_17 & !N_15 & !N_16 & !N_10 & !N_11 & !N_12
            # N_10 & N_11 & N_16 & !N_17 & !N_15 & !N_12 & !N_13
            # N_11 & N_17 & !N_15 & !N_16 & !N_12 & !N_13
            # N_10 & N_13 & N_14 & !N_17 & !N_15 & !N_12
            # N_10 & N_11 & N_17 & !N_15 & !N_16 & !N_13
            # N_15 & !N_17 & !N_16 & !N_11 & !N_12
            # N_12 & N_14 & !N_15 & !N_16 & !N_11
            # OR_1116)
            $ (N_12 & N_14 & !N_15 & !N_16 & !N_10 & !N_13 & !OR_1116
            # N_10 & N_13 & N_14 & !N_17 & !N_16 & !N_11 & !OR_1116
            # N_15 & !N_17 & !N_16 & !N_10 & !N_12 & !N_13 & !OR_1116
            # N_10 & N_17 & !N_15 & !N_16 & !N_14 & !N_12 & !N_13
            & !OR_1116
            # N_10 & N_11 & N_13 & N_14 & N_16 & !N_17 & !N_12 & !OR_1116
            # N_13 & N_15 & !N_17 & !N_16 & !N_14 & !N_11 & !N_12
            & !OR_1116)

    Output BUF_1197

        1 Input(s)
            CPX
        3 Fanout(s)
            glb06.CLK2, glb05.CLK2, glb03_part2.CLK2
        1 Product Term(s)
        1 GLB Level(s)

        BUF_1197 = CPX


GLB glb01, B3

    8 Input(s)
        (glb03_part2.O2, N_10, I9), (glb05.O3, N_11, I12), (glb06.O3, 
        N_12, I4), (glb06.O1, N_13, I6), (glb03_part2.O0, N_14, I11), 
        (glb05.O2, N_15, I13), (glb05.O1, N_16, I14), (glb05.O0, 
        N_17, I15)
    2 Output(s)
        (JS_PIN, O1), (CS_PIN, O2)
    19 Product Term(s)

    Output JS_PIN

        8 Input(s)
            N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            JS.IR
        9 Product Term(s)
        1 GLB Level(s)

        JS_PIN = (N_14 & N_16 & !N_17 & !N_11 & !N_12 & !N_13
            # N_14 & N_15 & N_16 & !N_17 & !N_12 & !N_13
            # N_12 & N_13 & N_15 & !N_17 & !N_16 & !N_14
            # !N_17 & !N_15 & !N_16 & !N_14 & !N_12 & !N_13
            # N_14 & N_16 & !N_17 & !N_10 & !N_12 & !N_13
            # N_11 & N_12 & N_13 & N_16 & !N_17 & !N_15 & !N_14
            # N_14 & N_15 & !N_17 & !N_10 & !N_11 & !N_12 & !N_13
            # N_14 & N_15 & N_16 & !N_17 & !N_10 & !N_11 & !N_13
            # !N_17 & !N_15 & !N_16 & !N_14 & !N_10 & !N_11 & !N_13)

    Output CS_PIN

        8 Input(s)
            N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            CS.IR
        10 Product Term(s)
        1 GLB Level(s)

        CS_PIN = (N_11 & N_13 & N_16 & !N_17 & !N_15 & !N_14
            # N_10 & N_11 & N_12 & N_13 & N_17 & !N_15 & !N_16
            # N_10 & N_12 & N_13 & N_17 & !N_15 & !N_16 & !N_14
            # N_11 & N_12 & N_13 & N_17 & !N_15 & !N_16 & !N_14
            # N_10 & N_13 & N_16 & !N_17 & !N_14 & !N_11 & !N_12
            # N_13 & N_15 & N_16 & !N_17 & !N_14 & !N_10 & !N_12
            # N_10 & N_11 & N_12 & N_15 & !N_17 & !N_16 & !N_14 & !N_13
            )
            $ (N_14 & N_17 & !N_15 & !N_16
            # N_13 & N_15 & !N_17 & !N_14 & !N_12
            # N_12 & N_13 & N_16 & !N_17 & !N_14)


GLB glb02, B1

    7 Input(s)
        (glb05.O3, N_11, I12), (glb06.O3, N_12, I4), (glb06.O1, 
        N_13, I6), (glb03_part2.O0, N_14, I11), (glb05.O2, N_15, I13), 
        (glb05.O1, N_16, I14), (glb05.O0, N_17, I15)
    2 Output(s)
        (QX_PIN, O2), (FZ_PIN, O0)
    18 Product Term(s)

    Output QX_PIN

        7 Input(s)
            N_17, N_11, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            QX.IR
        5 Product Term(s)
        1 GLB Level(s)

        QX_PIN = (N_16 & !N_17
            # N_14 & N_15 & !N_17
            # N_17 & !N_15 & !N_16 & !N_14
            # N_12 & N_13 & N_15 & !N_17
            # N_17 & !N_15 & !N_16 & !N_11 & !N_12 & !N_13)

    Output FZ_PIN

        7 Input(s)
            N_17, N_11, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            FZ.IR
        13 Product Term(s)
        1 GLB Level(s)

        FZ_PIN = (N_13 & N_15 & N_16 & !N_17 & !N_11 & !N_12
            # N_11 & N_12 & N_16 & !N_17 & !N_15 & !N_13
            # N_12 & N_15 & !N_17 & !N_16 & !N_11 & !N_13
            # N_11 & N_13 & N_17 & !N_15 & !N_16 & !N_14 & !N_12
            # N_12 & N_17 & !N_15 & !N_16 & !N_14 & !N_11 & !N_13
            # N_11 & N_12 & N_13 & N_14 & N_15 & N_16 & !N_17
            # N_11 & N_15 & N_16 & !N_17 & !N_14 & !N_12 & !N_13
            # N_12 & N_13 & N_14 & N_16 & !N_17 & !N_15 & !N_11
            # N_16 & !N_17 & !N_15 & !N_14 & !N_11 & !N_12 & !N_13
            # N_11 & N_13 & N_14 & N_15 & !N_17 & !N_16 & !N_12
            # N_11 & N_12 & N_13 & N_14 & !N_17 & !N_15 & !N_16
            # N_13 & N_14 & !N_17 & !N_15 & !N_16 & !N_11 & !N_12
            # N_11 & N_14 & !N_17 & !N_15 & !N_16 & !N_12 & !N_13)


GLB glb03_part1, B6

    6 Input(s)
        (glb06.O3, N_12, I4), (glb06.O1, N_13, I6), (glb03_part2.O0, 
        N_14, I11), (glb05.O2, N_15, I13), (glb05.O1, N_16, I14), 
        (glb05.O0, N_17, I15)
    1 Output(s)
        (XI_PIN, O1)
    5 Product Term(s)

    Output XI_PIN

        6 Input(s)
            N_17, N_12, N_13, N_14, N_15, N_16
        1 Fanout(s)
            XI.IR
        3 Product Term(s)
        1 GLB Level(s)

        XI_PIN = !N_17 & !N_15 & !N_16
            # !N_17 & !N_16 & !N_14 & !N_12
            # !N_17 & !N_16 & !N_14 & !N_13


GLB glb03_part2, A5

    8 Input(s)
        (glb03_part2.O2, N_10, I16), (glb05.O3, N_11, I3), (glb06.O3, 
        N_12, I11), (glb06.O1, N_13, I9), (glb03_part2.O0, N_14, I4), 
        (glb05.O2, N_15, I2), (glb05.O1, N_16, I1), (glb05.O0, 
        N_17, I0)
    2 Output(s)
        (N_14, O0), (N_10, O2)
    11 Product Term(s)

    Output N_14

        8 Input(s)
            N_17, N_10, N_11, N_12, N_13, N_14, N_15, N_16
        7 Fanout(s)
            glb05.I4, glb03_part2.I4, glb04.I4, glb00.I11, glb02.I11,
            glb01.I11, glb03_part1.I11
        8 Product Term(s)
        1 GLB Level(s)

        N_14.D = (!N_14 & !N_10
            # !N_14 & !N_11
            # !N_14 & !N_12
            # !N_14 & !N_13
            # N_15 & N_17
            # N_16 & N_17
            # N_10 & N_11 & N_12 & N_13 & N_14)
            $ VCC
        N_14.C = BUF_1197
        N_14.R = 
    Output N_10