wash.log

洗衣机的程序 洗衣机的程序

ispEXPERT Compiler Release 6.1.00.37.42.06, May 20 2002 13:06:40

Copyright (C) 1994-2000 by Lattice Semiconductor Corporation.
All Rights Reserved.


Design Process Management 

Renaming existing log file to wash.lo-
Renaming existing rpt file to wash.rp-

Preprocessing design 'wash'...

Processing design 'wash'...


Logical LAF Reading and Translation 
  
Reading file 'e:\wash\wash.laf'... 
  
Checking design rules... 
Selected part is 'ispLSI1016-60LH44/883' 
32581 WARNING: Option 'SLOWSLEW OFF' is not valid for part 
      'ispLSI1016-60LH44/883'; option 'SLOWSLEW OFF' is ignored 
  
Writing output files... 
  
Logical LAF reading and translation completed successfully 


Synthesis and Partitioning 
  
Reading design 'wash'... 
  
Optimizing logic... 
33583 WARNING: Data input of register 'N_18' is connected to GND; 
      register is removed 
  
Trying to move PT reset signal to global reset pin... 
      PT reset signal cannot be moved to global reset pin because there 
      exists no PT reset signal 
      In order to move PT reset signal to global reset pin, the 
      following conditions need to be satisfied: 
      1. There exists at least one pin which drives all register's reset
      signals 
      2. This pin is unlocked 
      3. This pin does not drive any data signals 
      4. This pin can be disjointly decomposed with other pins, if any, 
      which drive reset signals 
  
Partitioning logic into 16-input, 16-input with DIs, functions to 
      minimize delay... 
  
Extracting LXOR2 gates to minimize delay... 
  
Packing functions into GLBs using 16 inputs and 4 outputs per GLB to 
      minimize delay... 
  
Synthesis and partitioning statistics: 
  
Number of Macrocells is 18 
Number of GLBs is 7 
Number of product terms is 112 
Maximum number of GLB levels is 2 
Average number of inputs per GLB is 8.0 
Average number of outputs per GLB is 2.6 
Average number of product terms per GLB is 16.0 
  
Synthesis and partitioning completed successfully 


Physical LAF Reading and Translation

Reading design 'wash'...

Writing output files...

Physical LAF reading and translation completed successfully


Placement and Routing

Reading design 'wash'...

Routing
.


Writing output files...

Placement and routing completed successfully


Technology Remapping 
  
Reading design 'wash'... 
  
Remapping... 
  
Writing output files... 
  
Writing output lco files... 
  
Technology remapping completed successfully 


Physical LAF Reading and Translation

Reading design 'wash'...

Writing output files...

Physical LAF reading and translation completed successfully


Fusemap Generation

Reading design 'wash'...

Writing output files...

Fusemap generation completed successfully


Simulation LAF Netlist Generation

Reading design 'wash'...

Writing output files...


Information: Global reset (XRESET) is generated to reset all registers



Simulation LAF netlist generation completed successfully


Timing Analyzer 
Reading design wash .... 

Evaluating maximum operating frequency...
Evaluating setup and hold times...
43006 WARNING: No chip input pins drive data input and clock input of any register

Calculating  Tpd Path delays ...

........

              
     
Timing analyzer completed successfully 



Lattice Verilog netlist writer
Copyright (c) 1993 - 2000 by Lattice Semiconductor Corporation.
All Rights Reserved.

writing verilog netlist ...

Verilog netlist writer completed successfully.



Lattice VHDL netlist writer
Copyright (c) 1993 - 2000 by Lattice Semiconductor Corporation.
All Rights Reserved.

writing vhdl file ...
VHDL netlist writer completed successfully.


Design process management completed successfully