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📄 os_cpu_a.lst

📁 这个是我将UCOS移植到LPC系列的基本模版,大家可以下载下来参考下,和ZLG的完全不一样,并不是采用软中断实现任务切换,更加稳定.如果有问题可以rayeryanglei@126.com
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  363 00000064         OS_CPU_FIQ_ISR_1



ARM Macro Assembler    Page 10 


  364 00000064 E321F0D1        MSR              CPSR_c, #(NO_INT | FIQ32_MODE) 
                                                            ; Change to FIQ mod
                                                            e (touse the FIQ st
                                                            ack to handle inter
                                                            rupt)
  365 00000068 E28DD010        ADD              SP, SP, #16 ; Adjust FIQ stack 
                                                            pointer (Working re
                                                            gister were saved)
  366 0000006C E59F0064        LDR              R0, LAB_OS_CPU_FIQ_ISR_Handler 
                                                            ; OS_CPU_FIQ_ISR_Ha
                                                            ndler();
  367 00000070 E1A0E00F        MOV              LR, PC
  368 00000074 E12FFF10        BX               R0
  369 00000078         
  370 00000078 E321F0D3        MSR              CPSR_c, #(NO_INT | SVC32_MODE) 
                                                            ; Change to SVC mod
                                                            e
  371 0000007C E59F0058        LDR              R0, LAB_OS_IntExit 
                                                            ; OSIntExit();
  372 00000080 E1A0E00F        MOV              LR, PC
  373 00000084 E12FFF10        BX               R0
  374 00000088         
  375 00000088         ; RESTORE NEW TASK'S CONTEXT
  376 00000088 E8BD0010        LDMFD            SP!, {R4}   ;    Pop new task's
                                                             CPSR
  377 0000008C E16FF004        MSR              SPSR_cxsf, R4
  378 00000090         
  379 00000090 E8FDDFFF        LDMFD            SP!, {R0-R12,LR,PC}^ ;    Pop n
                                                            ew task's context 
  380 00000094         
  381 00000094         
  382 00000094         ; =============== FIQ interrupted IRQ ===============
  383 00000094         OS_CPU_FIQ_ISR_2
  384 00000094         ; SAVE IRQ'S CONTEXT ONTO FIQ'S STACK
  385 00000094 E92D40FF        STMFD            SP!, {R0-R7,LR} ;    Push share
                                                            d registers
  386 00000098         ; HANDLE NESTING COUNTER
  387 00000098 E59F0040        LDR              R0, LAB_OS_IntNesting ; OSIntNe
                                                            sting++;    (Notify
                                                             uC/OS-II)
  388 0000009C E5D01000        LDRB             R1, [R0]
  389 000000A0 E2811001        ADD              R1, R1,#1
  390 000000A4 E5C01000        STRB             R1, [R0]
  391 000000A8         
  392 000000A8         
  393 000000A8 E59F0028        LDR              R0, LAB_OS_CPU_FIQ_ISR_Handler 
                                                            ; OS_CPU_FIQ_ISR_Ha
                                                            ndler();
  394 000000AC E1A0E00F        MOV              LR, PC
  395 000000B0 E12FFF10        BX               R0
  396 000000B4         ; HANDLE NESTING COUNTER
  397 000000B4 E59F0024        LDR              R0, LAB_OS_IntNesting 
                                                            ; OSIntNesting--;
  398 000000B8 E5D01000        LDRB             R1, [R0]    ;   NO need to call
                                                             OSIntExit() we are
                                                             returning to IRQ h
                                                            andler
  399 000000BC E2411001        SUB              R1, R1, #1
  400 000000C0 E5C01000        STRB             R1, [R0]



ARM Macro Assembler    Page 11 


  401 000000C4         
  402 000000C4 E8BD40FF        LDMFD            SP!, {R0-R7,LR} 
                                                            ; Pop IRQ's context
                                                            
  403 000000C8 E8BD001E        LDMFD            SP!, {R1-R4} ; PULL WORKING REG
                                                            ISTERS ONTO FIQ STA
                                                            CK
  404 000000CC E25EF004        SUBS             PC, LR, #4  ; Return to IRQ
  405 000000D0         
  406 000000D0         
  407 000000D0         ;*******************************************************
                       **************************************************
  408 000000D0         ;                                     POINTERS TO VARIAB
                       LES
  409 000000D0         ;*******************************************************
                       **************************************************
  410 000000D0         
  411 000000D0         DATA
  412 000000D0         
  413 000000D0         LAB_OS_TaskSwHook
  414 000000D0 00000000        DCD              OSTaskSwHook
  415 000000D4         
  416 000000D4         LAB_OS_CPU_IRQ_ISR_Handler
  417 000000D4 00000000        DCD              OS_CPU_IRQ_ISR_Handler
  418 000000D8         
  419 000000D8         LAB_OS_CPU_FIQ_ISR_Handler
  420 000000D8 00000000        DCD              OS_CPU_FIQ_ISR_Handler
  421 000000DC         
  422 000000DC         LAB_OS_IntExit
  423 000000DC 00000000        DCD              OSIntExit
  424 000000E0         
  425 000000E0         LAB_OS_IntNesting
  426 000000E0 00000000        DCD              OSIntNesting
  427 000000E4         
  428 000000E4         LAB_OS_PrioCur
  429 000000E4 00000000        DCD              OSPrioCur
  430 000000E8         
  431 000000E8         LAB_OS_PrioHighRdy
  432 000000E8 00000000        DCD              OSPrioHighRdy
  433 000000EC         
  434 000000EC         LAB_OS_Running
  435 000000EC 00000000        DCD              OSRunning
  436 000000F0         
  437 000000F0         LAB_OS_TCBCur
  438 000000F0 00000000        DCD              OSTCBCur
  439 000000F4         
  440 000000F4         LAB_OS_TCBHighRdy
  441 000000F4 00000000        DCD              OSTCBHighRdy
  442 000000F8         
  443 000000F8                 END
Command Line: --debug --xref --device=DARMP --apcs=interwork -o.\output\db_eram
_bank1\os_cpu_a.o -IC:\Keil\ARM\INC\Philips --predefine="DB_ERAM_BANK1 SETA 1" 
--predefine="REMAP SETA 1" --predefine="RAM_MODE SETA 1" --predefine="EXTERNAL_
MODE SETA 1" --predefine="VIC_COPY1 SETA 1" --list=.\output\db_eram_bank1\os_cp
u_a.lst source\arm\os_cpu_a.asm



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE1 00000000

Symbol: CODE1
   Definitions
      At line 86 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE1 unused
OS_CPU_SR_Restore 00000020

Symbol: OS_CPU_SR_Restore
   Definitions
      At line 105 in file source\arm\os_cpu_a.asm
   Uses
      At line 32 in file source\arm\os_cpu_a.asm
Comment: OS_CPU_SR_Restore used once
OS_CPU_SR_Save 00000000

Symbol: OS_CPU_SR_Save
   Definitions
      At line 94 in file source\arm\os_cpu_a.asm
   Uses
      At line 31 in file source\arm\os_cpu_a.asm
      At line 101 in file source\arm\os_cpu_a.asm

3 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE2 00000000

Symbol: CODE2
   Definitions
      At line 120 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE2 unused
OSStartHighRdy 00000000

Symbol: OSStartHighRdy
   Definitions
      At line 126 in file source\arm\os_cpu_a.asm
   Uses
      At line 33 in file source\arm\os_cpu_a.asm
Comment: OSStartHighRdy used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE3 00000000

Symbol: CODE3
   Definitions
      At line 167 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE3 unused
OSCtxSw 00000000

Symbol: OSCtxSw
   Definitions
      At line 172 in file source\arm\os_cpu_a.asm
   Uses
      At line 34 in file source\arm\os_cpu_a.asm
Comment: OSCtxSw used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE4 00000000

Symbol: CODE4
   Definitions
      At line 226 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE4 unused
OSIntCtxSw 00000000

Symbol: OSIntCtxSw
   Definitions
      At line 231 in file source\arm\os_cpu_a.asm
   Uses
      At line 35 in file source\arm\os_cpu_a.asm
Comment: OSIntCtxSw used once
2 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE5 00000000

Symbol: CODE5
   Definitions
      At line 258 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE5 unused
OS_CPU_IRQ_ISR 00000000

Symbol: OS_CPU_IRQ_ISR
   Definitions
      At line 263 in file source\arm\os_cpu_a.asm
   Uses
      At line 36 in file source\arm\os_cpu_a.asm
Comment: OS_CPU_IRQ_ISR used once
OS_CPU_IRQ_ISR_1 0000005C

Symbol: OS_CPU_IRQ_ISR_1
   Definitions
      At line 296 in file source\arm\os_cpu_a.asm
   Uses
      At line 290 in file source\arm\os_cpu_a.asm
Comment: OS_CPU_IRQ_ISR_1 used once
3 symbols



ARM Macro Assembler    Page 1 Alphabetic symbol ordering
Relocatable symbols

CODE6 00000000

Symbol: CODE6
   Definitions
      At line 319 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: CODE6 unused
DATA 000000D0

Symbol: DATA
   Definitions
      At line 411 in file source\arm\os_cpu_a.asm
   Uses
      None
Comment: DATA unused
LAB_OS_CPU_FIQ_ISR_Handler 000000D8

Symbol: LAB_OS_CPU_FIQ_ISR_Handler
   Definitions
      At line 419 in file source\arm\os_cpu_a.asm
   Uses
      At line 366 in file source\arm\os_cpu_a.asm
      At line 393 in file source\arm\os_cpu_a.asm

LAB_OS_CPU_IRQ_ISR_Handler 000000D4

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