📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2006,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; Generic ARM
Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V1.70
12 00000000 ; By : Jean J. Labrosse
13 00000000 ;
14 00000000 ; For : ARM7 or ARM9
15 00000000 ; Mode : ARM or Thumb
16 00000000 ; Toolchain : IAR's EWARM V4.11a and higher
17 00000000 ;*******************************************************
*************************************************
18 00000000
19 00000000 EXTERN OSRunning ; External referenc
es
20 00000000 EXTERN OSPrioCur
21 00000000 EXTERN OSPrioHighRdy
22 00000000 EXTERN OSTCBCur
23 00000000 EXTERN OSTCBHighRdy
24 00000000 EXTERN OSIntNesting
25 00000000 EXTERN OSIntExit
26 00000000 EXTERN OSTaskSwHook
27 00000000 EXTERN OS_CPU_IRQ_ISR_Handler
28 00000000 EXTERN OS_CPU_FIQ_ISR_Handler
29 00000000
30 00000000
31 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
32 00000000 EXPORT OS_CPU_SR_Restore
33 00000000 EXPORT OSStartHighRdy
34 00000000 EXPORT OSCtxSw
35 00000000 EXPORT OSIntCtxSw
36 00000000 EXPORT OS_CPU_IRQ_ISR
37 00000000 EXPORT OS_CPU_FIQ_ISR
38 00000000
39 00000000
40 00000000 000000C0
NO_INT EQU 0xC0 ; Mask used to disa
ble interrupts (Bot
h FIR and IRQ)
41 00000000 00000080
NO_IRQ EQU 0x80 ; Mask used to disa
ble interrupts (Bot
h FIR and IRQ)
42 00000000 00000040
NO_FIQ EQU 0x40 ; Mask used to disa
ble interrupts (Bot
ARM Macro Assembler Page 2
h FIR and IRQ)
43 00000000 00000013
SVC32_MODE
EQU 0x13
44 00000000 00000011
FIQ32_MODE
EQU 0x11
45 00000000 00000012
IRQ32_MODE
EQU 0x12
46 00000000
47 00000000
48 00000000
49 00000000
50 00000000 ;*******************************************************
**************************************************
51 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
52 00000000 ;
53 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
54 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
55 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
56 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
57 00000000 ; into the CPU's status register.
58 00000000 ;
59 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
60 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
61 00000000 ;
62 00000000 ;
63 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
64 00000000 ;
65 00000000 ; void Task (void *p_arg)
66 00000000 ; {
67 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
68 00000000 ; OS_CPU_SR cpu_sr;
69 00000000 ; #endif
70 00000000 ;
71 00000000 ; :
72 00000000 ; :
73 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
74 00000000 ; :
75 00000000 ; :
76 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
77 00000000 ; :
78 00000000 ; :
79 00000000 ; }
80 00000000 ;
81 00000000 ; 2) OS_CPU_SaveSR() is implemented as reco
mmended by Atmel's application note:
82 00000000 ;
ARM Macro Assembler Page 3
83 00000000 ; "Disabling Interrupts at Processor
Level"
84 00000000 ;*******************************************************
**************************************************
85 00000000 PRESERVE8
86 00000000 AREA CODE1,CODE,READONLY
87 00000000 ARM
88 00000000 ; RSEG CODE:CODE:NOROOT(2)
89 00000000 ; CODE32
90 00000000
91 00000000
92 00000000
93 00000000
94 00000000 OS_CPU_SR_Save
95 00000000 E10F0000 MRS R0,CPSR ; Set IRQ and FIQ b
its in CPSR to disa
ble all interrupts
96 00000004 E38010C0 ORR R1,R0,#NO_INT
97 00000008 E121F001 MSR CPSR_c,R1
98 0000000C E10F1000 MRS R1,CPSR ; Confirm that CPSR
contains the prope
r interrupt disable
flags
99 00000010 E20110C0 AND R1,R1,#NO_INT
100 00000014 E35100C0 CMP R1,#NO_INT
101 00000018 1AFFFFFE BNE OS_CPU_SR_Save ; Not properly d
isabled (try again)
102 0000001C E12FFF1E BX LR ; Disabled, return
the original CPSR c
ontents in R0
103 00000020
104 00000020
105 00000020 OS_CPU_SR_Restore
106 00000020 E121F000 MSR CPSR_c,R0
107 00000024 E12FFF1E BX LR
108 00000028
109 00000028
110 00000028 ;*******************************************************
**************************************************
111 00000028 ; START MULTITA
SKING
112 00000028 ; void OSStartHigh
Rdy(void)
113 00000028 ;
114 00000028 ; Note(s) : 1) OSStartHighRdy() MUST:
115 00000028 ; a) Call OSTaskSwHook() then,
116 00000028 ; b) Set OSRunning to TRUE,
117 00000028 ; c) Switch to the highest priority task.
118 00000028 ;*******************************************************
**************************************************
119 00000028
120 00000028 AREA CODE2,CODE,READONLY
121 00000000 ARM
122 00000000
123 00000000 ; RSEG CODE:CODE:NOROOT(2)
124 00000000 ; CODE32
125 00000000
126 00000000 OSStartHighRdy
ARM Macro Assembler Page 4
127 00000000
128 00000000 E51F0008 LDR R0, LAB_OS_TaskSwHook
; OSTaskSwHook();
129 00000004 E1A0E00F MOV LR, PC
130 00000008 E12FFF10 BX R0
131 0000000C
132 0000000C E32FF0D3 MSR CPSR_cxsf, #0xD3 ; Switch to SV
C mode with IRQ and
FIQ disabled
133 00000010
134 00000010 E51F4008 LDR R4, LAB_OS_Running
; OSRunning = TRUE
135 00000014 E3A05001 MOV R5, #1
136 00000018 E5C45000 STRB R5, [R4]
137 0000001C
138 0000001C ; SWITCH TO HIGHEST PRIORITY TASK
139 0000001C E51F4008 LDR R4, LAB_OS_TCBHighRdy ; Get
highest priority ta
sk TCB address
140 00000020 E5944000 LDR R4, [R4] ; get stack poin
ter
141 00000024 E594D000 LDR SP, [R4] ; switch to the
new stack
142 00000028
143 00000028 E49D4004 LDR R4, [SP], #4 ; pop new task
's CPSR
144 0000002C E16FF004 MSR SPSR_cxsf,R4
145 00000030 E8FDDFFF LDMFD SP!, {R0-R12,LR,PC}^ ; pop n
ew task's context
146 00000034
147 00000034
148 00000034 ;*******************************************************
**************************************************
149 00000034 ; PERFORM A CONTEXT SWITCH (From
task level) - OSCtxSw()
150 00000034 ;
151 00000034 ; Note(s) : 1) OSCtxSw() is called in SYS mode with BOTH
FIQ and IRQ interrupts DISABLED
152 00000034 ;
153 00000034 ; 2) The pseudo-code for OSCtxSw() is:
154 00000034 ; a) Save the current task's context onto t
he current task's stack
155 00000034 ; b) OSTCBCur->OSTCBStkPtr = SP;
156 00000034 ; c) OSTaskSwHook();
157 00000034 ; d) OSPrioCur = OSPrioHighRdy;
158 00000034 ; e) OSTCBCur = OSTCBHighRdy;
159 00000034 ; f) SP = OSTCBHighRdy->
OSTCBStkPtr;
160 00000034 ; g) Restore the new task's context from th
e new task's stack
161 00000034 ; h) Return to new task's code
162 00000034 ;
163 00000034 ; 3) Upon entry:
164 00000034 ; OSTCBCur points to the OS_TCB of the
task to suspend
165 00000034 ; OSTCBHighRdy points to the OS_TCB of the
task to resume
166 00000034 ;*******************************************************
ARM Macro Assembler Page 5
**************************************************
167 00000034 AREA CODE3,CODE,READONLY
168 00000000 ARM
169 00000000 ; RSEG CODE:CODE:NOROOT(2)
170 00000000 ; CODE32
171 00000000
172 00000000 OSCtxSw
173 00000000 ; SAVE CURRENT TASK'S CONTEXT
174 00000000 E92D4000 STMFD SP!, {LR} ; Push return a
ddress
175 00000004 E92D4000 STMFD SP!, {LR}
176 00000008 E92D1FFF STMFD SP!, {R0-R12} ; Push regist
ers
177 0000000C E10F4000 MRS R4, CPSR ; Push current
CPSR
178 00000010 E31E0001 TST LR, #1 ; See if called
from Thumb mode
179 00000014 13844020 ORRNE R4, R4, #0x20 ; If yes, Se
t the T-bit
180 00000018 E92D0010 STMFD SP!, {R4}
181 0000001C
182 0000001C E51F4008 LDR R4, LAB_OS_TCBCur ; OSTCBCur->O
STCBStkPtr = SP;
183 00000020 E5945000 LDR R5, [R4]
184 00000024 E585D000 STR SP, [R5]
185 00000028
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