📄 pci.h
字号:
/******************************************************************************/
/*FILENAME: PCI.H */
/*DESCRIPTION: This file provides the header for the PCI Controller */
/* CY7C09449 support. */
/******************************************************************************/
#ifndef _PCI_H_
#define _PCI_H_
/*----------------------------------------------------------------------------*/
/* INCLUDES */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif
#define PCI_BASIC 0xA0000000
#define SMEMORY_OFFSET 0x4000
#define SMEMORY_SZ 0x4000
/*----------------------------------------------------------------------------*/
/* REGISTERS OFFSET DEFINES */
/*----------------------------------------------------------------------------*/
#define I2OHISR 0x0030 /*I2O Host Interrupt Status Register */
#define I2OHIMR 0x0034 /*I2O Host Interrupt Mask Register */
#define I2OLISR 0x0038 /*I2O Local Interrupt Status Register */
#define I2OLIMR 0x003C /*I2O Local Interrupt Mask Register */
/* I2O FIFO Access all default as empty FIFO, read as 0xFFFFFFFF */
#define IBFPFIFO 0x0040 /*Inbound Free FIFO (read only) and Inbound Post FIFO (write only)*/
#define OBPFFIFO 0x0044 /*Outbound Post FIFO(read only) and Outbound Free FIFO(write only)*/
#define IBPFFIFO 0x0048 /*Inbound Post FIFO (read only) and Inbound Free FIFO (write only)*/
#define OBFPFIFO 0x004C /*Outbound Free FIFO(read only) and Outbound Post FIFO(write only)*/
/* Direct Access Register */
#define DAHBASE 0x0460 /*Direct Access Host Physical Base Address Register*/
/* I2C Serial Port Registers */
#define NVCMD 0x04A0 /*I2C serial command register */
#define NVREAD 0x04A4 /*I2C serial read data register */
#define NVSTAT 0x04A8 /*I2C serial status register */
/* PCI Bus Mastering (DMA) Registers */
#define DMALBASE 0x04B0 /*DMA Local Base Address(16 Kbyte) Register */
#define DMAHBASE 0x04B4 /*DMA Host Base Address(4 Gbyte) Register */
#define DMASIZE 0x04B8 /*DMA Burst Size (16K byte)Register */
#define DMACTL 0x04BC /*DMA Control Register */
#define ARBUTIL 0x04C0 /*Arbitration Utility Flag Register */
/* Host Control and Status Registers */
#define HCTL 0x04E0 /*Host Control bit0 -Local Processor Reset */
#define HINT 0x04E4 /*Host Interrupt Control/Status */
#define HLDATA 0x04E8 /*Host to Local Data Mailbox */
/* Local Control and Status Registers */
#define LINT 0x04F4 /*Local Processor Interrupt Control/Status */
#define LHDATA 0x04F8 /*Local to Host Data Mailbox */
#define LBUSCFG 0x04FC /*Local Bus Configuration */
/*----------------------------------------------------------------------------*/
/*Local Interrupt Control/Status (LINT) Bitfield Description */
/*----------------------------------------------------------------------------*/
/* Interrupt Enables bit[25:16] */
/* Note: All enable bits are initially cleared. */
/*00 0000 0000 = no interrupts are enabled (default) */
/*xx xxxx xxx1 = I2O Local FIFO overflow interrupt enabled */
/*xx xxxx xx1x = I2O PCI FIFO overflow interrupt enabled */
/*xx xxxx x1xx = reserved - always read as 0 */
/*xx xxxx 1xxx = Host to Local mailbox interrupt enabled */
/*xx xxx1 xxxx = reserved - always read as 0 */
/*xx xx1x xxxx = DMA complete interrupt enabled */
/*xx x1xx xxxx = I2O inbound post FIFO not empty interrupt enabled */
/*xx 1xxx xxxx = I2O outbound post FIFO not empty interrupt enabled */
/*x1 xxxx xxxx = PCI target abort interrupt enabled */
/*1x xxxx xxxx = PCI master abort interrupt enabled */
/* Interrupt Event Status bit[9:0] */
/*Note:All event status bits are initially cleared. */
/* When an event status bit is active,writing a '1' to that */
/* bit location will clear the bit except for bits 6 and 7. */
/*00 0000 0000 = no events active */
/*xx xxxx xxx1 = I2O Local FIFO overflow */
/*xx xxxx xx1x = I2O PCI FIFO overflow */
/*xx xxxx x1xx = reserved - always read as 0 */
/*xx xxxx 1xxx = Host to Local mailbox */
/*xx xxx1 xxxx = reserved - always read as 0 */
/*xx xx1x xxxx = DMA operation complete */
/*xx x1xx xxxx = I2O inbound post FIFO not empty */
/* (mirror of I2OLISR[3] - read only at this address) */
/*xx 1xxx xxxx = I2O outbound post FIFO not empty */
/* (mirror of I2OHISR[3] - read only at this address) */
/*x1 xxxx xxxx = PCI target abort */
/*1x xxxx xxxx = PCI master abort */
/*----------------------------------------------------------------------------*/
/* LBUSCFG Bit Description */
/*----------------------------------------------------------------------------*/
#define DDOUT 0 /*Delayed Data Output:Defines protocol for validated output data. */
#define DDIN 1 /*Delayed Data Input:Defines protocol for validated input data. */
#define ASMODE 2 /*Bit 2 defines the polarity of STROBE input signal.And bit 3 defines the edge */
#define ASMODE_SZ 2 /* of CLKIN used to sample the Internal Address Strobe.*/
#define RWMODE 4 /*Defines how the READ, WRITE, and address STROBE input signals are interpreted*/
#define RWMODE_SZ 2 /* internally and define the Internal Address Strobe.*/
#define BEMODE 6 /*Determines the byte enable encoding for 16 and 32 bit Motorola modes. */
#define BLASTMODE 7 /*Determines the function of the BLAST input signal. */
#define BW 8 /*Defines the data bus width of the local processor interface. */
#define BW_SZ 2
#define RDYOUT_POL 10 /*Defines the polarity of the RDY_OUT output signal. */
#define ALE_POL 11 /*Defines the polarity of the ALE input signal. */
#define BLAST_POL 12 /*Defines the polarity of the BLAST input signal. */
#define INT_POL 13 /*Defines the polarity of the IRQ_OUT output signal. */
#define BURST_STYLE 14 /*Defines the data ordering protocol of bursts on the local bus. */
#define XTND_RDY_OUT 15 /*Defines the RDY_OUT output signal relation to the final data phase. */
#define RDY_OUT_OE 16 /*Defines the three-state mode of the RDY_OUT output signal. */
#define SELECT_FALL 17 /*Defines the edge of CLKIN used to sample the SELECT input signal. */
#define SELECT_POL 18 /*Defines the polarity of the SELECT input signal. */
#define RDY_IN_FALL 19 /*Defines the edge of CLKIN used to sample the RDY_IN and RDY_IN input signals.*/
#define LINE_WRAP_DIS 20 /*Defines the enable for cache line wrapping. */
/*----------------------------------------------------------------------------*/
/* NVCMD Bit Description */
/*----------------------------------------------------------------------------*/
#define R_W 0 /* 1 = read command;0 = write command */
#define READ_TYPE 1 /* 1 = 4-byte read;0 = single-byte read */
#define WRITE_DATA 8
#define WRITE_DATA_SZ 8
#define MEM_ADDR 16 /* Address within the I2C serial device */
#define MEM_ADDR_SZ 8
#define DEV_ADDR 26 /* Device address of the I2C serial device. Default is 1010000.*/
#define DEV_ADDR_SZ 7
/*----------------------------------------------------------------------------*/
/* NVSTAT Bit Description */
/*----------------------------------------------------------------------------*/
#define DONE 0 /* Done Indicator:1 = done;0 = in progress */
#define ACK 5 /* bit 7 = device address ack bit. 0 = ack, 1 = no ack. */
/* bit 6 = address ack bit. 0 = ack, 1 = no ack. */
/* bit 5 = second address ack bit. 0 = ack, 1 = no ack. */
/* In a successful read or write, these bits will be 000.*/
#define ACK_SZ 3
/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS */
/*----------------------------------------------------------------------------*/
#define I2C_DEVADDR_WRITE(dev_addr)\
LOAD_FIELD((PCI_BASIC+NVCMD),dev_addr,DEV_ADDR,DEV_ADDR_SZ)
#define I2C_MEMADDR_WRITE(mem_addr)\
LOAD_FIELD((PCI_BASIC+NVCMD),mem_addr,MEM_ADDR,MEM_ADDR_SZ)
#define I2C_DATA_WRITE(data)\
LOAD_FIELD((PCI_BASIC+NVCMD),data,MEM_ADDR,MEM_ADDR_SZ)
#define I2C_DONE_POLL GET_BIT((PCI_BASIC+NVSTAT),DONE)
#define I2C_ACK_POLL GET_FIELD((PCI_BASIC+NVSTAT),ACK,ACK_SZ)
#define I2C_DATA_READ REG_READ(PCI_BASIC+NVREAD)
#define ENABLE_LOCAL_INTR(intr)\
SET_BIT((PCI_BASIC+LINT),(intr+16))
#define DISABLE_LOCAL_INTR(intr)\
RESET_BIT((PCI_BASIC+LINT),(intr+16))
#define LOCAL_INTR_POLL(intr)\
GET_BIT((PCI_BASIC+LINT),intr)
#define LOCAL_INTR_CLR(intr)\
SET_BIT((PCI_BASIC+LINT),intr)
#define ENABLE_HOST_INTR(intr)\
SET_BIT((PCI_BASIC+HINT),(intr+16))
#define DISABLE_HOST_INTR(intr)\
RESET_BIT((PCI_BASIC+HINT),(intr+16))
#define HOST_INTR_POLL(intr)\
GET_BIT((PCI_BASIC+HINT),intr)
#define HOST_INTR_CLR(intr)\
SET_BIT((PCI_BASIC+HINT),intr)
/*----------------------------------------------------------------------------*/
/* FUNCTIONS */
/*----------------------------------------------------------------------------*/
/* Set read type: type=1---4-byte read; type=0---single-byte read */
static inline void i2c_read_type(unsigned char type)
{
if(type==1)
SET_BIT((PCI_BASIC+NVCMD),READ_TYPE);
else if(type==0)
RESET_BIT((PCI_BASIC+NVCMD),READ_TYPE);
}
/* Set operation type: type=1---read command;type=0---write command */
static inline void i2c_start_operation(unsigned char type)
{
if(type==1)
SET_BIT((PCI_BASIC+NVCMD),R_W);
else if(type==0)
RESET_BIT((PCI_BASIC+NVCMD),R_W);
}
#endif /* _PCI_H*/
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -