📄 mcbsp.h
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/******************************************************************************/
/* McBSP.H - TMS320C6711 Peripheral Support Library McBSP Support */
/* */
/* This file provides the header for the DSP's McBSP support. */
/******************************************************************************/
#ifndef _McBSP_H_
#define _McBSP_H_
/*----------------------------------------------------------------------------*/
/* INCLUDES */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif
/*----------------------------------------------------------------------------*/
/* DEFINES */
/*----------------------------------------------------------------------------*/
/* Define McBSP0 Registers */
#define McBSP0_DRR 0x18c0000 /* Address of data receive reg. */
#define McBSP0_DXR 0x18c0004 /* Address of data transmit reg. */
#define McBSP0_SPCR 0x18c0008 /* Address of serial port contl. reg. */
#define McBSP0_RCR 0x18c000C /* Address of receive control reg. */
#define McBSP0_XCR 0x18c0010 /* Address of transmit control reg. */
#define McBSP0_SRGR 0x18c0014 /* Address of sample rate generator */
#define McBSP0_MCR 0x18c0018 /* Address of multichannel reg. */
#define McBSP0_RCER 0x18c001C /* Address of receive channel enable. */
#define McBSP0_XCER 0x18c0020 /* Address of transmit channel enable. */
#define McBSP0_PCR 0x18c0024 /* Address of pin control reg. */
/* Define McBSP1 Registers */
#define McBSP1_DRR 0x1900000 /* Address of data receive reg. */
#define McBSP1_DXR 0x1900004 /* Address of data transmit reg. */
#define McBSP1_SPCR 0x1900008 /* Address of serial port contl. reg. */
#define McBSP1_RCR 0x190000C /* Address of receive control reg. */
#define McBSP1_XCR 0x1900010 /* Address of transmit control reg. */
#define McBSP1_SRGR 0x1900014 /* Address of sample rate generator */
#define McBSP1_MCR 0x1900018 /* Address of multichannel reg. */
#define McBSP1_RCER 0x190001C /* Address of receive channel enable. */
#define McBSP1_XCER 0x1900020 /* Address of transmit channel enable. */
#define McBSP1_PCR 0x1900024 /* Address of pin control reg. */
/*McBSP Serial Port Control Register (McBSP_SPCR) Bitfield*/
#define PRST 0 /*Receiver reset. */
#define PRDY 1 /*Receiver ready */
#define RFULL 2 /*Receive shift register (RSR) full error condition*/
#define RSYNCERR 3 /*Receive synchronization error */
#define RINTM 4 /*Receive interrupt mode */
#define RINTM_SZ 2
#define DXENA 7 /*Enable extra delay for DX turn-on time.*/
#define CLKSTP 11 /*Clock stop mode */
#define CLKSTP_SZ 2
#define RJUST 13 /*Receive data sign-extension and justification mode*/
#define RJUST_SZ 2
#define DLB 15 /*Digital loopback mode */
#define XRST 16 /*Transmitter reset */
#define XRDY 17 /*Transmitter ready */
#define XEMPTY 18 /*Transmit shift register (XSR) empty*/
#define XSYNCERR 19 /*Transmit synchronization error */
#define XINTM 20 /*Transmit interrupt mode */
#define XINTM_SZ 2
#define GRST 22 /*Sample rate generator reset */
#define FRST 23 /*Frame sync generator reset */
#define SOFT 24 /*Serial clock emulation mode */
#define FREE 25 /*Serial clock free running mode */
/*McBSP Receive Control Register (McBSP_RCR) Bitfield*/
#define RWDREVRST 4 /*Receive 32-bit bit reversal feature.*/
#define RWDLEN1 5 /*Receive element length in phase 1 */
#define RWDLEN1_SZ 3
#define RFRLEN1 8 /*Receive frame length in phase 1 */
#define RFRLEN1_SZ 7
#define RDATDLY 16 /*Receive data delay */
#define RDATDLY_SZ 2
#define RFIG 18 /*Receive frame ignore */
#define RCOMPAND 19 /*Receive companding mode. */
#define RCOMPAND_SZ 2
#define RWDLEN2 21 /*Receive element length in phase 2 */
#define RWDLEN2_SZ 3
#define RFRLEN2 24 /*Receive frame length in phase 2 */
#define RFRLEN2_SZ 7
#define RPHASE 31 /*Receive phases */
/*McBSP Transmit Control Register (McBSP_XCR) Bitfield*/
#define XWDREVRST 4 /*Transmit 32-bit bit reversal feature*/
#define XWDLEN1 5 /*Transmit element length in phase 1 */
#define XWDLEN1_SZ 3
#define XFRLEN1 8 /*Transmit frame length in phase 1 */
#define XFRLEN1_SZ 7
#define XDATDLY 16 /*Transmit data delay */
#define XDATDLY_SZ 2
#define XFIG 18 /*Transmit frame ignore */
#define XCOMPAND 19 /*Transmit companding mode. */
#define XCOMPAND_SZ 2
#define XWDLEN2 21 /*Transmit element length in phase 2 */
#define XWDLEN2_SZ 3
#define XFRLEN2 24 /*Transmit frame length in phase 2 */
#define XFRLEN2_SZ 7
#define XPHASE 31 /*Transmit phases */
/*McBSP Sample Rate Generator Register (McBSP_SRGR) Bitfield*/
#define CLKGDV 0 /*Sample rate generator clock divider. */
#define CLKGDV_SZ 8
#define FWID 8 /*Frame width. */
#define FWID_SZ 8
#define FPER 16 /*Frame period. */
#define FPER_SZ 12
#define FSGM 28 /*Sample rate generator transmit frame synchronization mode.*/
#define CLKSM 29 /*McBSP sample rate generator clock mode */
#define CLKSP 30 /*CLKS polarity clock edge select. */
#define GSYNC 31 /*Sample rate generator clock synchronization.*/
/*McBSP Pin Control Register (McBSP_PCR) Bitfield*/
#define CLKRP 0 /*Receive clock polarity */
#define CLKXP 1 /*Transmit clock polarity */
#define FSRP 2 /*Receive frame synchronization polarity */
#define FSXP 3 /*Transmit frame synchronization polarity*/
#define DR_STAT 4 /*DR pin status. */
#define DX_STAT 5 /*DX pin status. */
#define CLKS_STAT 6 /*CLKS pin status. */
#define CLKRM 8 /*Receiver clock mode */
#define CLKXM 9 /*Transmitter clock mode */
#define FSRM 10 /*Receive frame synchronization mode */
#define FSXM 11 /*Transmit frame synchronization mode */
#define RIOEN 12 /*Receiver in general-purpose I/O mode only when RRST = 0 in SPCR */
#define XIOEN 13 /*Transmitter in general-purpose I/O mode only when XRST = 0 in SPCR*/
/*McBSP Multichannel Control Register (McBSP_MCR) Bitfield*/
#define RMCM 0 /*Receive multichannel selection enable*/
#define RCBLK 2 /*Receive current subframe */
#define RCBLK_SZ 3
#define RPABLK 5 /*Receive partition A subframe */
#define RPABLK_SZ 2
#define RPBBLK 7 /*Receive partition B subframe */
#define RPBBLK_SZ 2
#define XMXM 16 /*Transmit multichannel selection enable*/
#define XMCM_SZ 2
#define XCBLK 18 /*Transmit current subframe */
#define XCBLK_SZ 3
#define XPABLK 21 /*Transmit partition A subframe */
#define XPABLK_SZ 2
#define XPBBLK 23 /*Transmit partition B subframe */
#define XPBBLK_SZ 2
/*McBSP Transmit Channel Enable Register(McBSP_XCER) Bitfield*/
#define XCEA0 0 /*XCEAn Transmit channel enable */
/*XCEA n = 0: Disables transmission of the nth element in*/
/* an even-numbered subframe in partition A */
/*XCEA n = 1: Enables transmission of the nth element in */
/* an even-numbered subframe in partition A */
#define XCEB0 16 /*Transmit channel enable */
/*XCEA n = 0: Disables transmission of the nth element in*/
/* an even-numbered subframe in partition B */
/*XCEA n = 1: Enables transmission of the nth element in */
/* an even-numbered subframe in partition B */
/*McBSP Transmit Channel Enable Register(McBSP_RCER) Bitfield*/
#define RCEA0 0 /*Receive channel enable */
/* RCE n = 0: Disables reception of the nth channel */
/* RCE n = 1: Enables reception of the nth channel. */
#define RCEB0 16
/*----------------------------------------------------------------------------*/
/* TIMER0 MACRO FUNCTIONS */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* FUNCTIONS: */
/*----------------------------------------------------------------------------*/
#endif /* _TIMER_H_ */
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