📄 emif.h
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/******************************************************************************/
/* EMIF.H - TMS320C6711 Peripheral Support Library EMIF Support */
/* */
/* This file provides the header for the DSP's EMIF support. */
/******************************************************************************/
#ifndef _EMIF_H_
#define _EMIF_H_
/*----------------------------------------------------------------------------*/
/* INCLUDES */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif
/*----------------------------------------------------------------------------*/
/* DEFINES */
/*----------------------------------------------------------------------------*/
/* Define EMIF Registers */
#define EMIF_GBLCTL 0x1800000 /* Address of EMIF global control */
#define EMIF_CECTL0 0x1800008 /* Address of EMIF CE0 Space control */
#define EMIF_CECTL1 0x1800004 /* Address of EMIF CE1 Space control */
#define EMIF_CECTL2 0x1800010 /* Address of EMIF CE2 Space control */
#define EMIF_CECTL3 0x1800014 /* Address of EMIF CE3 Space control */
#define EMIF_SDCTL 0x1800018 /* Address of EMIF SDRAM control */
#define EMIF_SDTIM 0x180001c /* Address of EMIF SDRM refresh control */
#define EMIF_SDEXT 0x1800020 /* Address of EMIF SDRAM extension */
/* EMIF Memory Space Map */
#define EMIF_CE0_BEGIN 0x80000000 /* BEGIN of EMIF CE0 control */
#define EMIF_CE1_BEGIN 0x90000000 /* BEGIN of EMIF CE1 control */
#define EMIF_CE2_BEGIN 0xA0000000 /* BEGIN of EMIF CE2 control */
#define EMIF_CE3_BEGIN 0xB0000000 /* BEGIN of EMIF CE3 control */
#define EMIF_CE0_END 0x8FFFFFFF /* END of EMIF CE0 control */
#define EMIF_CE1_END 0x9FFFFFFF /* END of EMIF CE1 control */
#define EMIF_CE2_END 0xAFFFFFFF /* END of EMIF CE2 control */
#define EMIF_CE3_END 0xBFFFFFFF /* END of EMIF CE3 control */
/* EMIF global control(EMIF_GBLCTL) Bitfield */
#define CLK2EN 3 /*CLKOUT2 enable*/
#define CLK1EN 4 /*CLKOUT1 enable*/
#define NOHOLD 7 /*External HOLD disable*/
#define HOLDA 8 /**/
#define HOLD 9 /**/
#define ARDY 10 /**/
#define BUSREQ 11 /**/
/* EMIF CEx Space control (EMIF_CECTLx) Bitfield*/
#define READ_HOLD 0 /**/
#define READ_HOLD_SZ 2
/* add */
#define DEVCFG 0x019c0200 /* device config register */
#define PLLCSR 0x01B7C100 /* PLL Control/Status Register */
#define PLLM 0x01B7C110 /*PLL Multiplier Control Register */
#define GPEN 0x01B00000 /*GPIO Enable Register () */
#define GPDIR 0x01B00004 /*GPIO Direction Register */
#define PLLDIV0 0x01B7C114 /*PLL Wrapper Divider x Registers*/
#define PLLDIV1 0x01B7C118
#define PLLDIV2 0x01B7C11C
#define PLLDIV3 0x01B7C120
#define SCDIV1 0x01B7C124/*Oscillator Divider 1 control clkout3 no use */
/*Memory type of the corresponding CE spaces*/
/*MTYPE = 0000b: 8-bit-wide asynchronous interface */
/*MTYPE = 0001b: 16-bit-wide asynchronous interface*/
/*MTYPE = 0010b: 32-bit-wide asynchronous interface*/
/*MTYPE = 0011b: 32-bit-wide SDRAM */
/*MTYPE = 0100b: 32-bit-wide SBSRAM (C621x/C671x) */
/*MTYPE = 1000b: 8-bit-wide SDRAM */
/*MTYPE = 1001b: 16-bit-wide SDRAM */
/*MTYPE = 1010b: 8-bit-wide SBSRAM (C621x/C671x) */
/*MTYPE = 1011b: 16-bit-wide SBSRAM (C621x/C671x) */
/* EMIF CE Space Control Register Bitfield Values */
#define MTYPE_8ROM 0x00 /* 8 bit wide ROM */
#define MTYPE_16ROM 0x01 /* 16 bit wide ROM */
#define MTYPE_32ASYNC 0x02 /* 32 bit asynchronous interface */
#define MTYPE_32SDRAM 0x03 /* 32 bit SDRAM */
#define MTYPE_32SBSRAM 0x04 /* 32 bit SBSRAM */
#define MTYPE 4
#define MTYPE_SZ 4
#define READ_STROBE 8 /**/
#define READ_STROBE_SZ 6
#define TA 14 /*Turn-around time*/
#define TA_SZ 2
#define READ_SETUP 16 /**/
#define READ_SETUP_SZ 4
#define WRITE_HOLD 20 /**/
#define WRITE_HOLD_SZ 2
#define WRITE_STROBE 22 /**/
#define WRITE_STROBE_SZ 6
#define WRITE_SETUP 28 /**/
#define WRITE_SETUP_SZ 4
/* EMIF SDRAM control (EMIF_SDCTL) Bitfield*/
#define TRC 12 /*Specifies the tRC value of the */
#define TRC_SZ 4 /* SDRAM in EMIF clock cycles */
#define TRP 16 /*Specifies the tRP value of the */
#define TRP_SZ 4 /* SDRAM in EMIF clock cycles */
#define INIT 24 /*Forces initialization of all SDRAM present*/
#define RFEN 25 /*Refresh enable */
#define SDCSZ 26 /*SDRAM column size */
#define SDCSZ_SZ 2
#define SDRSZ 28 /*SDRAM row size */
#define SDRSZ_SZ 2
#define SDBSZ 30 /*SDRAM bank size */
/* EMIF SDRM refresh period (EMIF_SDTIM) Bitfield*/
#define PERIOD 0 /*Refresh period in EMIF clock cycles*/
#define PERIOD_SZ 12
#define COUNTER 12 /*Current value of the refresh counter*/
#define COUNTER_SZ 12
#define XRFR 24 /*Extra refreshes: controls the number of refreshes */
#define XRFR_SZ 2 /*performed to SDRAM when the refresh counter expires*/
/* EMIF SDRAM extension (EMIF_SDEXT) Bitfield*/
#define TCL 0 /*Specified CAS latency of the SDRAM in ECLKOUT cycles*/
#define TRAS 1 /*Specifies tRAS value of the SDRAM in ECLKOUT cycles*/
#define TRAS_SZ 3
#define TRRD 4 /*Specifies tRRD value of the SDRAM in ECLKOUT cycles*/
#define TWR 5 /*Specifies tWR value of the SDRAM in ECLKOUT cycles*/
#define TWR_SZ 2
#define THZP 7 /*Specifies tHZP (also known as tROH) value of */
#define THZP_SZ 2 /* the SDRAM in ECLKOUT cycles */
#define RD2RD 9 /*Specifies number of cycles between READ to READ command */
/* (same CE space) of theSDRAM in ECLKOUT cycles */
#define RD2DEAC 10 /*Specifies number of cycles between READ to DEAC/DCAB */
#define RD2DEAC_SZ 2 /* of the SDRAM in ECLKOUT cycles */
#define RD2WR 12 /*Specifies number of cycles between READ to WRITE */
/* command of the SDRAM in ECLKOUTcycles */
#define RD2WR_SZ 3
#define R2WDQM 15 /*Specifies number of of cycles that BEx signals must */
/* be high preceding a WRITE interruptinga READ */
#define R2WDQM_SZ 2
#define WR2WR 17 /*Specifies minimum number of cycles between WRITE to */
/* WRITE command of the SDRAM in ECLKOUT cycles*/
#define WR2DEAC 18 /*Specifies minimum number of cycles between WRITE to*/
/* DEAC/DCAB command of the SDRAM in ECLKOUT cycles*/
#define WR2DEAC_SZ 2
#define WR2RD 20 /*Specifies minimum number of cycles between WRITE to READ*/
/* command of the SDRAM in ECLKOUT cycles*/
/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS */
/*----------------------------------------------------------------------------*/
#define SDRAM_REFRESH_ENABLE() SET_BIT(EMIF_SDCTL,RFEN)
#define SDRAM_REFRESH_DISABLE() RESET_BIT(EMIF_SDCTL,RFEN)
#define SDRAM_REFRESH_PERIOD(val) LOAD_FIELD(EMIF_SDTIM,val,PERIOD,PERIOD_SZ)
#define SDRAM_INIT() SET_BIT(EMIF_SDCTL,INIT)
#endif /* _EMIF_H*/
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