📄 edm.h
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/******************************************************************************/
/* EDMA.H - TMS320C6711 Peripheral Support Library EMIF Support */
/* */
/* This file provides the header for the DSP's EMIF support. */
/******************************************************************************/
#ifndef _EDMA_H_
#define _EDMA_H_
/*----------------------------------------------------------------------------*/
/* INCLUDES */
/*----------------------------------------------------------------------------*/
#ifndef MASTER_FILE
#define C6711_GLOBALS
#include "C6711_CPU.H"
#endif
/*----------------------------------------------------------------------------*/
/* DEFINES */
/*----------------------------------------------------------------------------*/
/* Define EDMA Registers */
#define PQSR 0x01A0FFE0 /* Address of priority queue status */
#define CIPR 0x01A0FFE4 /* Address of channel interrupt pending */
#define CIER 0x01A0FFE8 /* Address of channel interrupt enable */
#define CCER 0x01A0FFEC /* Address of channel chain enable */
#define ER 0x01A0FFF0 /* Address of event register */
#define EER 0x01A0FFF4 /* Address of event enable register */
#define ECR 0x01A0FFF8 /* Address of event clear register */
#define ESR 0x01A0FFFC /* Address of event set register */
/*EDMA Parameter RAM Contents Addresses*/
#define PaEVENT_SZ 24 /*(6 words)*/
#define EDMA_EVENT_PARAMETER(event) (0x01A00000 + (event*PaEVENT_SZ))
/* Address of Parameters for event */
/*The C6711 device has 85 EDMA parameters total: */
/* 16 Event/Reload parameters and 69 Reload-only parameters */
/*From 0x01A007F8h to 0x01A007FFh is Scratch pad area (2 words) */
/* Define EDMA Transfer Parameter Entry Fields */
#define EDMA_OPT 0 /* Transfer configuration Options Parameter */
#define EDMA_SRC 4 /* SRC Address Parameter */
#define EDMA_CNT 8
#define EDMA_ELECNT 0 /* The number of elements per frame */
#define EDMA_FRMCNT 16 /* The number of frames/arrays per block minus one */
#define EDMA_DST 12 /* DST Address Parameter */
#define EDMA_IDX 16
#define EDMA_ELEIDX 16 /* The address offset of elements within a frame */
#define EDMA_FRMIDX 18 /* The address offset of frames/arrays within a block */
#define EDMA_LINK_ELERLD 20
#define EDMA_LINK 0 /* The PaRAM address containing the parameter set to be linked*/
#define EDMA_ELERLD 16 /* The count value to be loaded at the end of each frame */
/* Define EDMA Option Parameter (OPT) Bitfield*/
#define OPT_FS 0 /* Frame synchronization */
#define OPT_LINK 1 /* Linking of event parameters */
#define OPT_TCC 16 /* Transfer complete code */
#define OPT_TCC_SZ 4
#define OPT_TCINT 20 /* Transfer complete interrupt */
#define OPT_DUM 21 /* Destination address update mode */
#define OPT_DUM_SZ 2
#define OPT_2DD 23 /* Destination dimension */
#define OPT_SUM 24 /* Source address update mode */
#define OPT_SUM_SZ 2
#define OPT_2DS 26 /* Source dimension */
#define OPT_ESIZE 27 /* Element size */
#define OPT_ESIZE_SZ 2
#define OPT_PRI 29 /* Priority levels for EDMA events */
#define OPT_PRI_SZ 3 /* 001b Level1: high priority */
/* 010b Level2: low priority */
/* EDMA Channel Synchronization Events*/
#define EVENT_DSP_INT 0 /*Host to DSP interrupt */
#define EVENT_TINT0 1 /*Timer 0 interrupt */
#define EVENT_TINT1 2 /*Timer 1 interrupt */
#define EVENT_SD_INT 3 /*EMIF SDRAM timer interrupt */
#define EVENT_EXT_INT4 4 /*External interrupt pin 4 */
#define EVENT_EXT_INT5 5 /*External interrupt pin 5 */
#define EVENT_EXT_INT6 6 /*External interrupt pin 6 */
#define EVENT_EXT_INT7 7 /*External interrupt pin 7 */
#define EVENT_EDMA_TCC8 8 /*EDMA transfer complete code 1000b interrupt*/
#define EVENT_EDMA_TCC9 9 /*EDMA transfer complete code 1001b interrupt*/
#define EVENT_EDMA_TCC10 10 /*EDMA transfer complete code 1010b interrupt*/
#define EVENT_EDMA_TCC11 11 /*EDMA transfer complete code 1011b interrupt*/
#define EVENT_XEVT0 12 /*McBSP0 transmit event */
#define EVENT_REVT0 13 /*McBSP0 receive event */
#define EVENT_XEVT1 14 /*McBSP1 transmit event */
#define EVENT_REVT1 15 /*McBSP1 receive event */
/******************************************************************************
* The priority queue status register (PQSR) indicates whether the transfer
* request queue is empty on the priority level queues. Status bits PQ in the
* PQSR provide the status of the queues.
* EDMA Priority Queue status Register(PQSR) Bitfield PQ[0:2]=0:2
* Transfer Request Queues Total Length (fixed) and its Maximum Queue Length
********************************************************************************/
/* Available to Requester */
#define PQ0_MAX 6 /* L2 controller 6 */
#define PQ1_MAX 13 /* EDMA:8; QDMA:3; HPI:2 */
#define PQ2_MAX 11 /* EDMA:8; QDMA:3 */
/* Channel Interrupt Enable Register (CIER)---CIE[0:15]= 0:15 */
/* EDMA Event Register(ER) ---EVT[0:15]= 0:15 */
/* EDMA Event Enable Register(EER) ---EE[0:7] = 0:7,EE[12:15] = 12:15 */
/* EDMA Channel Chain Enable Register(CCER)---CCE[8:11]= 8:11 */
/* Event Set Register (ESR) ---ES[0:15] = 0:15 */
/* Event Clear Register (ECR) ---EC[0:15] = 0:15 */
/* EDMA Channel Interrupt Pending Register(CIPR)----CIP0[0:15]=0:15 */
/*----------------------------------------------------------------------------*/
/* MACRO FUNCTIONS */
/*----------------------------------------------------------------------------*/
#define EDMA_OPT_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_OPT)
#define EDMA_SRC_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_SRC)
#define EDMA_DST_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_DST)
#define EDMA_CNT_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_CNT)
#define EDMA_IDX_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_IDX)
#define EDMA_LINK_ELERLD_ADDR(chan) (EDMA_EVENT_PARAMETER(chan)+EDMA_LINK)
/* Assign EDMA Options Parameter (OPT) bitfields */
#define OPT_RWSYNC_SET(chan) RESET_BIT(EDMA_OPT_ADDR(chan),OPT_FS)
#define OPT_AFSYNC_SET(chan) SET_BIT(EDMA_OPT_ADDR(chan), OPT_FS)
#define OPT_SRC_1D(chan) RESET_BIT(EDMA_OPT_ADDR(chan),OPT_2DS)
#define OPT_SRC_2D(chan) SET_BIT(EDMA_OPT_ADDR(chan), OPT_2DS)
#define OPT_DST_1D(chan) RESET_BIT(EDMA_OPT_ADDR(chan),OPT_2DD)
#define OPT_DST_2D(chan) SET_BIT(EDMA_OPT_ADDR(chan), OPT_2DD)
#define OPT_TCINT_ENABLE(chan) SET_BIT(EDMA_OPT_ADDR(chan), OPT_TCINT)
#define OPT_TCINT_DISABLE(chan) RESET_BIT(EDMA_OPT_ADDR(chan),OPT_TCINT)
#define OPT_LINK_ENABLE(chan) SET_BIT(EDMA_OPT_ADDR(chan), OPT_LINK)
#define OPT_LINKT_DISABLE(chan) RESET_BIT(EDMA_OPT_ADDR(chan),OPT_LINK)
#define OPT_TCC_WRITE(chan,tcc)\
LOAD_FIELD(EDMA_OPT_ADDR(chan),tcc,OPT_TCC,OPT_TCC_SZ)
#define OPT_SUM_WRITE(chan,sum)\
LOAD_FIELD(EDMA_OPT_ADDR(chan),sum,OPT_SUM,OPT_SUM_SZ)
#define OPT_DUM_WRITE(chan,dum)\
LOAD_FIELD(EDMA_OPT_ADDR(chan),dum,OPT_DUM,OPT_DUM_SZ)
#define OPT_ESIZE_WRITE(chan,esize)\
LOAD_FIELD(EDMA_OPT_ADDR(chan),esize,OPT_ESIZE,OPT_ESIZE_SZ)
#define OPT_PRI_WRITE(chan,pri)\
LOAD_FIELD(EDMA_OPT_ADDR(chan),pri,OPT_PRI,OPT_PRI_SZ)
/* Read EDMA Options Parameter (OPT) bitfields */
#define OPT_FS_READ(chan) GET_BIT(EDMA_OPT_ADDR(chan), OPT_FS)
#define OPT_LINK_READ(chan) GET_BIT(EDMA_OPT_ADDR(chan), OPT_LINK)
#define OPT_2DS_READ(chan) GET_BIT(EDMA_OPT_ADDR(chan), OPT_2DS)
#define OPT_2DD_READ(chan) GET_BIT(EDMA_OPT_ADDR(chan), OPT_2DD)
#define OPT_TCINT_READ(chan) GET_BIT(EDMA_OPT_ADDR(chan), OPT_TCINT)
#define OPT_TCC_READ(chan)\
GET_FIELD(EDMA_OPT_ADDR(chan),OPT_TCC,OPTA_TCC_SZ)
#define OPT_SUM_READ(chan)\
GET_FIELD(EDMA_OPT_ADDR(chan),OPT_SUM,OPT_SUM_SZ)
#define OPT_DUM_READ(chan)\
GET_FIELD(EDMA_OPT_ADDR(chan),OPT_DUM,OPT_DUM_SZ)
#define OPT_ESIZE_READ(chan)\
GET_FIELD(EDMA_OPT_ADDR(chan),OPT_ESIZE,OPT_ESIZE_SZ)
#define OPT_PRI_READ(chan)\
GET_FIELD(EDMA_OPT_ADDR(chan),OPT_PRI,OPT_PRI_SZ)
/* Assign EDMA Parameter Set */
#define EDMA_OPT_WRITE(chan,opt) REG_WRITE(EDMA_OPT_ADDR(chan),opt)
#define EDMA_SRC_WRITE(chan,addr) REG_WRITE(EDMA_SRC_ADDR(chan),addr)
#define EDMA_DST_WRITE(chan,addr) REG_WRITE(EDMA_DST_ADDR(chan),addr)
#define EDMA_FRMCNT_WRITE(chan,frmcnt)\
LOAD_FIELD(EDMA_CNT_ADDR(chan),frmcnt,EDMA_FRMCNT,16)
#define EDMA_ELECNT_WRITE(chan,elecnt)\
LOAD_FIELD(EDMA_CNT_ADDR(chan),elecnt,EDMA_ELECNT,16)
#define EDMA_FRMIDX_WRITE(chan,frmidx)\
LOAD_FIELD(EDMA_IDX_ADDR(chan),frmidx,EDMA_FRMIDX,16)
#define EDMA_ELEIDX_WRITE(chan,eleidx)\
LOAD_FIELD(EDMA_IDX_ADDR(chan),eleidx,EDMA_ELEIDX,16)
#define EDMA_LINK_WRITE(chan,link)\
LOAD_FIELD(EDMA_LINK_ELERLD_ADDR(chan),link,EDMA_LINK,16)
#define EDMA_ELERLD_WRITE(chan,elerld)\
LOAD_FIELD(EDMA_LINK_ELERLD_ADDR(chan),elerld,EDMA_ELERLD,16)
/* Read EDMA Parameter Set */
#define EDMA_OPT_READ(chan) REG_READ(EDMA_OPT_ADDR(chan))
#define EDMA_SRC_READ(chan) REG_READ(EDMA_SRC_ADDR(chan))
#define EDMA_DST_READ(chan) REG_READ(EDMA_DST_ADDR(chan))
#define EDMA_ELECNT_READ(chan)\
((REG_READ(EDMA_CNT_ADDR(chan)))&0x0000FFFF)
#define EDMA_FRMCNT_READ(chan)\
(((REG_READ(EDMA_CNT_ADDR(chan)))>>16)&0x0000FFFF)
#define EDMA_ELEIDX_READ(chan)\
((REG_READ(EDMA_IDX_ADDR(chan)))&0x0000FFFF)
#define EDMA_FRMIDX_READ(chan)\
(((REG_READ(EDMA_IDX_ADDR(chan)))>>16)&0x0000FFFF)
#define EDMA_LINK_READ(chan)\
((REG_READ(EDMA_LINK_ELERLD_ADDR(chan)))&0x0000FFFF))
#define EDMA_ELERLD_READ(chan,link,elecnt)\
(((REG_READ(EDMA_LINK_ELERLD_ADDR(chan)))>>16)&0x0000FFFF)
#define EDMA_ASYNC_ENABLE(chan) SET_BIT(ESR,chan)
#define EDMA_ASYNC_DISABLE(chan) SET_BIT(ECR,chan)
#define EDMA_SYNC_ENABLE(chan) SET_BIT((((1<<chan)&0x0F00)?CCER:EER),chan)
#define EDMA_SYNC_DISABLE(chan) RESET_BIT((((1<<chan)&0x0F00)?CCER:EER),chan)
#define EDMA_CHAIN_ENABLE(chan) SET_BIT(CCER,chan)
#define EDMA_CHAIN_DISABLE(chan) RESET_BIT(CCER,chan)
#define EDMA_INT_ENABLE(chan) SET_BIT(CIER,chan)
#define EDMA_INT_DISABLE(chan) RESET_BIT(CIER,chan)
#define EDMA_INTFLAG_READ(chan) GET_BIT(CIPR,chan)
#define EDMA_INTFLAG_CLR(chan) RESET_BIT(CIPR,chan)
/*----------------------------------------------------------------------------*/
/* STATIC INLINE FUNCTIONS */
/*----------------------------------------------------------------------------*/
/* edma_get_chan()--return channel number corresponding to it entry addr */
static inline char edma_get_chan(unsigned int addr)
{
if(((addr-0x01A00000)%24)||(addr>=0x01A0017F))
{
return 0xff;
}
else return ((addr-0x01A00000)/24);
}
/* edma_pqsr_query()-- A '1' in the indicates that there no requests pending */
/* in the respective priority level queue. */
static inline BOOLEAN edma_pqsr_query(unsigned char pri)
{
if(GET_BIT(PQSR,pri))
{
return TRUE; /* No requests in this priority level */
}
else
return FALSE; /* There are requests in this priority level*/
}
#endif /* _EDMA_H*/
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