📄 boot.asm
字号:
.title "Flash bootup utility for 6211 dsk"
.option D,T
.length 102
.width 140
FLASH_USER .equ 0x90000400
DRAM_USER .equ 0x80000000
USER_SIZE .equ 0x00001B00
FLASH_REG1 .equ 0x90005555 ;address of the flash control reg 1
FLASH_REG2 .equ 0x90002AAA ;address of the flash control reg 2
FLASH_KEY1 .equ 0xAA
FLASH_KEY2 .equ 0x55
FLASH_KEY3 .equ 0xA0
IO_PORT .equ 0x90080000 ;address of I/O port, only top byte has valid data
EMIF_GCR .equ 0x01800000 ;EMIF global control
EMIF_CE1 .equ 0x01800004 ;address of EMIF CE1 control reg.
EMIF_CE0 .equ 0x01800008 ;EMIF CE0control
EMIF_SDCTRL .equ 0x01800018 ;EMIF SDRAM control
EMIF_SDTIM .equ 0x0180001c ;EMIF SDRM refresh period
EMIF_SDEXT .equ 0x01800020 ;Address of EMIF SDRAM extension
EMIF_CE1_8 .equ 0xffffff13 ;
EMIF_CE0_V .equ 0x00000030 ;EMIF CE0control ;0x30
EMIF_SDCTRL_V .equ 0x07126000 ;EMIF SDRAM control ;0x73380000
LED1 .equ 0x1940000 ;ctr0 timer0 bit2 4/0
LED0 .equ 0x1980000 ;ctr1 timer1 bit2
DEVCFG .equ 0x019c0200 ; device config register
PLLCSR .equ 0x01B7C100 ; PLL Control/Status Register
PLLM .equ 0x01B7C110 ;PLL Multiplier Control Register
PLLDIV0 .equ 0x01B7C114 ;PLL Wrapper Divider x Registers
PLLDIV1 .equ 0x01B7C118
PLLDIV2 .equ 0x01B7C11C
PLLDIV3 .equ 0x01B7C120
.sect ".boot_load"
.global _boot
;.ref _bootint00
.ref _c_int00
_boot:
MVK.S1 0x0109,A0
MVC.S2X A0,CSR
NOP
MVK.S1 0x0001,A0
MVC.S2X A0,IER
NOP
MVK.S2 0xffffc100,B4
MVKH.S2 0x1b70000,B4
LDW.D2T2 *+B4[0x0],B5
ZERO.D1 A0
SET.S1 A0,1,15,A0
NOP 2
AND.S2X B5,A0,B5
STW.D2T2 B5,*+B4[0x0]
NOP 4
MVK.S1 0xffffc100,A0
MVKH.S1 0x1b70000,A0
LDW.D1T1 *+A0[0x0],A3
NOP 4
OR.S1 8,A3,A3
STW.D1T1 A3,*+A0[0x0]
NOP 2
MVK.S1 0x7fff,A0
|| MVK.S2 0xffffc114,B4
ADD.D1 A0,0x2,A0
|| MVKH.S2 0x1b70000,B4
STW.D2T1 A0,*+B4[0x0]
NOP 8
MVK.S1 0xffffc110,A0
MVKH.S1 0x1b70000,A0
|| MVK.S2 0x0009,B4
STW.D1T2 B4,*+A0[0x0]
NOP 8
ZERO.D1 A0
|| MVK.S2 0xffffc118,B4
SET.S1 A0,15,15,A0
|| MVKH.S2 0x1b70000,B4
STW.D2T1 A0,*+B4[0x0]
NOP 8
MVK.S1 0xffffc11c,A0
|| ZERO.D2 B4
MVKH.S1 0x1b70000,A0
|| SET.S2 B4,15,15,B4
STW.D1T2 B4,*+A0[0x0]
NOP 8
MVK.S1 0x7fff,A0
|| MVK.S2 0xffffc120,B4
ADD.D1 A0,0x2,A0
|| MVKH.S2 0x1b70000,B4
STW.D2T1 A0,*+B4[0x0]
NOP 9
NOP 9
NOP 9
NOP 9
MVK.S2 0xffffc100,B4
MVKH.S2 0x1b70000,B4
LDW.D2T2 *+B4[0x0],B6
MVK.S2 0xfffffff7,B5
MVKH.S2 0x0000,B5
NOP 2
AND.S2 B5,B6,B5
STW.D2T2 B5,*+B4[0x0]
NOP 9
NOP 9
NOP 9
NOP 9
MVK.S1 0xffffc100,A0
MVKH.S1 0x1b70000,A0
LDW.D1T1 *+A0[0x0],A3
NOP 4
OR.S1 1,A3,A3
STW.D1T1 A3,*+A0[0x0]
NOP 2
MVK.S1 0x0200,A0
|| NOP
ZERO.D1 A3
|| MVKH.S1 0x19c0000,A0
STW.D1T1 A3,*+A0[0x0]
NOP 2
mvkl EMIF_GCR,A4 ;EMIF_GCR address ->A4
|| mvkl 0x3338,B4
mvkh EMIF_GCR,A4
|| mvkh 0x3338,B4
stw B4,*A4
mvkl EMIF_CE0,A4 ;EMIF_CE0 address ->A4
|| mvkl EMIF_CE0_V,B4 ;
mvkh EMIF_CE0,A4
|| mvkh EMIF_CE0_V,B4
stw B4,*A4
mvkl EMIF_CE1,A4 ;EMIF_CE0 address ->A4
|| mvkl EMIF_CE1_8,B4 ;
mvkh EMIF_CE1,A4
|| mvkh EMIF_CE1_8,B4
stw B4,*A4
|| mvkl EMIF_SDCTRL,A4 ;EMIF_SDCTRL address ->A4
|| mvkl EMIF_SDCTRL_V,B4 ;
mvkh EMIF_SDCTRL,A4
|| mvkh EMIF_SDCTRL_V,B4
stw B4,*A4
|| mvkl EMIF_SDTIM,A4 ;EMIF_SDTIMaddress ->A4
|| mvkl 0x61a,B4 ;
mvkh EMIF_SDTIM,A4
|| mvkh 0x61a,B4
stw B4,*A4
|| mvkl EMIF_SDEXT,A4 ;EMIF_SDEXT address ->A4
|| mvkl 0x54529,B4 ;
mvkh EMIF_SDEXT,A4
|| mvkh 0x54529,B4
stw B4,*A4
mvkl LED0,A4 ;LED0 oN
|| mvkl 0x0004,B4
mvkh LED0,A4
|| mvkh 0x0000,B4
stw B4,*A4
mvkl LED1,A4 ;LED1 oFF
|| mvkl 0x0000,B4
mvkh LED1,A4
|| mvkh 0x0000,B4
stw B4,*A4
;********************0x90000400--> 0x80000000
mvkl DRAM_USER,A4 ;apps code start address ->A4
|| mvkl FLASH_USER,B4 ;flash start address ->B4
mvkh DRAM_USER,A4
|| mvkh FLASH_USER,B4
zero A1
_boot_loop2:
ldb *B4++,B5
mvkl USER_SIZE,B6 ;B6 = BOOT_SIZE -1024
add 1,A1,A1 ;A1+=1,inc outer counter
|| mvkh USER_SIZE,B6
cmplt A1,B6,B0
nop 5
nop 5
stb B5,*A4++
[B0] b _boot_loop2
nop 5
;**********************************************
_leddelay:
mvkl .S2 _c_int00, B0;
mvkh .S2 _c_int00, B0;
B .S2 B0
nop 5
;
; end of the bootup routine
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