uart.c

手机GSM TI 平台 串口 uart 驱动 源代码

 *
 *                           UA_WriteNChars
 * 
 * Purpose  : Writes N characters in the TX FIFO.
 *
 * Arguments: In : uart_id       : UART id.
 *                 buffer        : buffer address from which characters are
 *                                 written.
 *                 bytes_to_write: number of bytes to write.
 *            Out: none
 *
 * Returns  : Number of bytes written.
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

SYS_UWORD32
UA_WriteNChars (T_tr_UartId uart_id,
                char *buffer,
                SYS_UWORD32 chars_to_write)
{
    SYS_UWORD32 chars_in_tx_fifo;
    SYS_UWORD32 chars_written;
    t_uart      *uart;

    chars_written = 0;
    uart = &(uart_parameter[uart_id]);

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Disable sleep mode.
     */

    WRITE_UART_REGISTER (
        uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
#endif

    /*
     * Copy the input buffer to the TX FIFO.
     * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
     * one period of Bclock => Workaround S/W.
     * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
     * while FIFO is not full.
     */

    if (READ_UART_REGISTER (uart, LSR) & THRE) {

        chars_in_tx_fifo = 0;

        while ((chars_written < chars_to_write) &&
               (chars_in_tx_fifo < FIFO_SIZE)) {

            WRITE_UART_REGISTER (uart, THR, *(buffer++));
            chars_written++;
            chars_in_tx_fifo++;
        }
    }

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Re-enable sleep mode.
     */

    WRITE_UART_REGISTER ( 
        uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
#endif

    return (chars_written);
}


/*******************************************************************************
 *
 *                           UA_EncapsulateNChars
 * 
 * Purpose  : Writes N characters in the TX FIFO in encapsulating them with 2
 *            STX bytes (one at the beginning and one at the end).
 *
 * Arguments: In : uart_id       : UART id.
 *                 buffer        : buffer address from which characters are
 *                                 written.
 *                 chars_to_write: number of chars to write.
 *            Out: none
 *
 * Returns  : Number of chars written.
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

SYS_UWORD32
UA_EncapsulateNChars (T_tr_UartId uart_id,
                      char *buffer,
                      SYS_UWORD32 chars_to_write)
{
    SYS_UWORD32 chars_written;
    SYS_UWORD32 chars_in_tx_fifo;
    t_uart      *uart;
    
    chars_written = 0;
    uart = &(uart_parameter[uart_id]);

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Disable sleep mode.
     */
              
    WRITE_UART_REGISTER (
        uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
#endif

    /*
     * Copy the input buffer to the TX FIFO.
     * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
     * one period of Bclock => Workaround S/W.
     * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
     * while FIFO is not full.
     */

    if (READ_UART_REGISTER (uart, LSR) & THRE) {

        chars_in_tx_fifo = 0;

        /*
         * Check if the message has been already encapsulated.
         */

        if (!uart->encapsulation_flag) {
            /*
             * Write STX in the TX FIFO and set the flag.
             */

            WRITE_UART_REGISTER (uart, THR, STX);
            chars_in_tx_fifo++;
            uart->encapsulation_flag = 1;
        }

        /*
         * Keep one char margin in the TX FIFO for the last STX.
         */

        while ((chars_written < chars_to_write) &&
               (chars_in_tx_fifo < (FIFO_SIZE-1))) {

            WRITE_UART_REGISTER (uart, THR, *(buffer++));
            chars_written++;
            chars_in_tx_fifo++;
        }

        /*
         * Append STX byte at the end if the frame is complete.
         */

        if (chars_written == chars_to_write) {

            /*
             * Write STX in the TX FIFO and reset the flag.
             */

            WRITE_UART_REGISTER (uart, THR, STX);
            uart->encapsulation_flag = 0;
        }
    }

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Re-enable sleep mode.
     */

    WRITE_UART_REGISTER ( 
        uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
#endif

    return (chars_written);
}


/*******************************************************************************
 *
 *                           UA_WriteNBytes
 * 
 * Purpose  : Writes N bytes in the TX FIFO in encapsulating with 2 STX bytes
 *            at the beginning and the end of the frame, and in making byte
 *            stuffing.
 *
 * Arguments: In : uart_id       : UART id.
 *                 buffer        : buffer address from which bytes are
 *                                 written.
 *                 bytes_to_write: number of bytes to write.
 *            Out: none
 *
 * Returns  : Number of bytes written.
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

SYS_UWORD32
UA_WriteNBytes (T_tr_UartId uart_id,
                SYS_UWORD8 *buffer,
                SYS_UWORD32 bytes_to_write)
{
    SYS_UWORD32 bytes_written;
    SYS_UWORD32 bytes_in_tx_fifo;
    t_uart      *uart;
        
    bytes_written = 0;
    uart = &(uart_parameter[uart_id]);

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Disable sleep mode.
     */
              
    WRITE_UART_REGISTER (
        uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
#endif

    /*
     * Copy the input buffer to the TX FIFO.
     * Ulyssse Bug #44: TX FIFO full status bit (SSR[1]) is corrupted during
     * one period of Bclock => Workaround S/W.
     * Write in TX FIFO only if FIFO is empty instead of writing in TX FIFO
     * while FIFO is not full.
     */

    if (READ_UART_REGISTER (uart, LSR) & THRE) {

        bytes_in_tx_fifo = 0;

        /*
         * Check if the message has been already encapsulated.
         */

        if (!uart->encapsulation_flag) {

            /*
             * Write STX in the TX FIFO and set the flag.
             */

            WRITE_UART_REGISTER (uart, THR, STX);
            bytes_in_tx_fifo++;
            uart->encapsulation_flag = 1;
        }

        /*
         * Keep 2 chars margin in the FIFO, one for the stuffing (if necessary)
         * and one for the last STX.
         */

        while ((bytes_written < bytes_to_write) && 
               (bytes_in_tx_fifo < (FIFO_SIZE-2))) {

            /*
             * Check for STX or DLE in order to perform the stuffing.
             */

            if ((*(buffer) == STX) || (*(buffer) == DLE)) {

                /*
                 * Write DLE in the TX FIFO.
                 */

                WRITE_UART_REGISTER (uart, THR, DLE);
                bytes_in_tx_fifo++;
            }

            WRITE_UART_REGISTER (uart, THR, *(buffer++));
            bytes_written++;
            bytes_in_tx_fifo++;
        }

        /*
         * Append STX byte at the end if the frame is complete.
         */

        if (bytes_written == bytes_to_write) {

            /*
             * Write STX in the TX FIFO and reset the flag.
             */

            WRITE_UART_REGISTER (uart, THR, STX);
            uart->encapsulation_flag = 0;
        }
    }

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Re-enable sleep mode.
     */

    WRITE_UART_REGISTER ( 
        uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
#endif

    return (bytes_written);
}


/*******************************************************************************
 *
 *                            UA_WriteChar
 * 
 * Purpose  : Writes a character in the TX FIFO.
 *
 * Arguments: In : uart: UART id.
 *                 character
 *            Out: none
 *
 * Returns  : none
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

void
UA_WriteChar (T_tr_UartId uart_id,
              char character)
{
    (void) UA_WriteNChars (uart_id, &character, 1);
}

/*******************************************************************************
 *
 *                          UA_WriteString
 * 
 * Purpose  : Writes a null terminated string in the TX FIFO.
 *
 * Arguments: In : uart_id: UART id.
 *                 buffer : buffer address from which characters are written.
 *            Out: none
 *
 * Returns  : none
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

void
UA_WriteString (T_tr_UartId uart_id,
                char *buffer)
{
    (void) UA_WriteNChars (uart_id, buffer, strlen (buffer));
}

/*******************************************************************************
 *
 *                             UA_EnterSleep
 * 
 * Purpose  : Checks if UART is ready to enter Deep Sleep. If ready, enables
 *            wake-up interrupt.
 *
 * Arguments: In : uart_id : UART id.
 *            Out: none
 *
 * Returns: 0    : Deep Sleep is not possible.
 *          >= 1 : Deep Sleep is possible.
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

SYS_BOOL
UA_EnterSleep (T_tr_UartId uart_id)
{
    t_uart              *uart;
    SYS_BOOL            deep_sleep;
    volatile SYS_UWORD8 status;
        
    uart = &(uart_parameter[uart_id]);
    deep_sleep = 0;

    /*
     * Check if RX & TX FIFOs are both empty
     */

    status = READ_UART_REGISTER (uart, LSR);

    if (!(status & DR) &&
        (status & TEMT)) {

#if ((CHIPSET != 5) && (CHIPSET != 6))
        /*
         * Disable sleep mode.
         */

        WRITE_UART_REGISTER (
            uart, IER, READ_UART_REGISTER (uart, IER) & ~IER_SLEEP);
#endif

        /*
         * Mask RX interrupt.
         */

        WRITE_UART_REGISTER (
            uart, IER, READ_UART_REGISTER (uart, IER) & ~ERBI);

        /*
         * Enable the wake-up interrupt.
         */

        ENABLE_WAKEUP_INTERRUPT (uart);

        deep_sleep = 1;
    }

    return (deep_sleep);
}

/*******************************************************************************
 *
 *                              UA_WakeUp
 * 
 * Purpose  : Wakes up UART after Deep Sleep.
 *
 * Arguments: In : uart_id : UART id.
 *            Out: none
 *
 * Returns: none
 *
 * Warning: Parameters are not verified.
 *
 ******************************************************************************/

void
UA_WakeUp (T_tr_UartId uart_id)
{
    t_uart *uart;

    uart = &(uart_parameter[uart_id]);

    /*
     * Disable the wake-up interrupt.
     */

    DISABLE_WAKEUP_INTERRUPT (uart);

    /*
     * Unmask RX interrupts.
     */

    WRITE_UART_REGISTER (
        uart, IER, READ_UART_REGISTER (uart, IER) | ERBI);

#if ((CHIPSET != 5) && (CHIPSET != 6))
    /*
     * Allow sleep mode.
     */

    WRITE_UART_REGISTER (
        uart, IER, READ_UART_REGISTER (uart, IER) | IER_SLEEP);
#endif
}

/*******************************************************************************
 *
 *                       UA_InterruptHandler
 * 
 * Purpose  : Interrupt handler.
 *
 * Arguments: In : uart_id         : origin of interrupt
 *                 interrupt_status: source of interrupt
 *            Out: none
 *
 * Returns  : none
 *
 ******************************************************************************/

void
UA_InterruptHandler (T_tr_UartId uart_id,
                     SYS_UWORD8 interrupt_status)
{
    t_uart *uart;
   
    uart = &(uart_parameter[uart_id]);

    switch (interrupt_status) {

        case RX_DATA:

            read_rx_fifo (uart);

        break;

        default:

#ifdef UART_RX_BUFFER_DUMP
            uart_rx_buffer_dump.wrong_interrupt_status++;
#endif

            /* No Processing */

        break;
    }
}