sys_dma.h

手机GSM TI 平台 dma 驱动 源代码

/*                @(#) nom : sys_dma.h SID: 1.2 date : 05/23/03               */
/* Filename:      sys_dma.h                                                   */
/* Version:       1.2                                                         */
/******************************************************************************
 *                   WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
 *
 *             (C) 2002 Texas Instruments France. All rights reserved
 *
 *                          Author : Guillaume Leterrier
 *                                   Francois Amand
 *
 *
 *  Important Note
 *  --------------
 *
 *  This S/W is a preliminary version. It contains information on a product 
 *  under development and is issued for evaluation purposes only. Features 
 *  characteristics, data and other information are subject to change.
 *
 *  The S/W is furnished under Non Disclosure Agreement and may be used or
 *  copied only in accordance with the terms of the agreement. It is an offence
 *  to copy the software in any way except as specifically set out in the 
 *  agreement. No part of this document may be reproduced or transmitted in any
 *  form or by any means, electronic or mechanical, including photocopying and
 *  recording, for any purpose without the express written permission of Texas
 *  Instruments Inc.
 *
 ******************************************************************************
 *
 *  FILE NAME: sys_dma.h
 *
 *
 *  PURPOSE:  Include file to use the DMA drivers for CALYPSO PLUS.
 *            The drivers allows DMA module configuration and control.
 *
 *
 *  FILE REFERENCES:
 *
 *  Name                  IO      Description
 *  -------------         --      ---------------------------------------------
 *  
 *
 *
 *  EXTERNAL VARIABLES:
 *
 *  Source:
 *
 *  Name                  Type              IO   Description
 *  -------------         ---------------   --   ------------------------------
 *
 *
 *
 *  EXTERNAL REFERENCES:
 *
 *  Name                Description
 *  ------------------  -------------------------------------------------------
 *
 *
 *
 *  ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
 *  
 *
 *
 *  ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
 *  
 *
 *
 *  NOTES:
 *  
 *
 *
 *  REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
 *
 *
 *
 *
 *  DEVELOPMENT HISTORY:
 *
 *  Date         Name(s)         Version  Description
 *  -----------  --------------  -------  -------------------------------------
 *  23-Oct-2002  Francois AMAND  0.0.1    First implementation
 *  23-Oct-2002  G.Leterrier     0.0.2    Type, prototype definition
 *   6-Dec-2002  G.Leterrier     0.0.3    remove base address
 *  24-Feb-2003  G.Leterrier     0.0.4    change base address include name
 *  ALGORITHM: 
 *  ALGORITHM: 
 *
 *
 *****************************************************************************/


#ifndef __SYS_DMA_H__
  #define __SYS_DMA_H__

  #include "chipset.cfg" 

  #if (CHIPSET == 12)

    #include "sys_types.h"

    #include "sys_map.h"
  
    /****************************************************************************
     *                            CONSTANT DEFINITION
     ***************************************************************************/
 



    #define C_DMA_VERSION_DRIVER                       0x0001

    #define C_DMA_NUMBER_OF_CHANNEL                   6
    
    /*
     *  Registers offset definition
     */

    #define C_DMA_CHANNEL_SELECT_POS                  6

    /* Global registers */
    #define C_DMA_GCR_OFFSET                          0x0400
    #define C_DMA_ISR_OFFSET                          0x0402
    #define C_DMA_CAR_OFFSET                          0x0404
    #define C_DMA_SCR_OFFSET                          0x0406
    #define C_DMA_SRR_OFFSET                          0x0408
    #define C_DMA_AR_OFFSET                           0x040A
    
    /* Channel registers */
    #define C_DMA_CSDP_OFFSET(d_channel_index)        (0x0000 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CCR_OFFSET(d_channel_index)         (0x0002 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CICR_OFFSET(d_channel_index)        (0x0004 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CSR_OFFSET(d_channel_index)         (0x0006 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CSSA_L_OFFSET(d_channel_index)      (0x0008 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CSSA_U_OFFSET(d_channel_index)      (0x000A + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CDSA_L_OFFSET(d_channel_index)      (0x000C + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CDSA_U_OFFSET(d_channel_index)      (0x000E + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CEN_OFFSET(d_channel_index)         (0x0010 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CFN_OFFSET(d_channel_index)         (0x0012 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
    #define C_DMA_CPC_OFFSET(d_channel_index)         (0x0018 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))


    /*
     *  Registers address definition
     */
    /* Global registers */
    #define C_DMA_GCR_REG                             * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_GCR_OFFSET)
    #define C_DMA_ISR_REG                             * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_ISR_OFFSET)
    #define C_DMA_CAR_REG                             * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CAR_OFFSET)
    #define C_DMA_SCR_REG                             * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_SCR_OFFSET)
    #define C_DMA_SRR_REG                             * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_SRR_OFFSET)
    #define C_DMA_AR_REG                              * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_AR_OFFSET)

    /* Channel registers */
    #define C_DMA_CSDP_REG(d_channel_index)           * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSDP_OFFSET(d_channel_index))
    #define C_DMA_CCR_REG(d_channel_index)            * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CCR_OFFSET(d_channel_index))
    #define C_DMA_CICR_REG(d_channel_index)           * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CICR_OFFSET(d_channel_index))
    #define C_DMA_CSR_REG(d_channel_index)            * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSR_OFFSET(d_channel_index))
    #define C_DMA_CSSA_L_REG(d_channel_index)         * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSSA_L_OFFSET(d_channel_index))
    #define C_DMA_CSSA_U_REG(d_channel_index)         * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSSA_U_OFFSET(d_channel_index))
    #define C_DMA_CDSA_L_REG(d_channel_index)         * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CDSA_L_OFFSET(d_channel_index))
    #define C_DMA_CDSA_U_REG(d_channel_index)         * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CDSA_U_OFFSET(d_channel_index))
    #define C_DMA_CEN_REG(d_channel_index)            * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CEN_OFFSET(d_channel_index))
    #define C_DMA_CFN_REG(d_channel_index)            * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CFN_OFFSET(d_channel_index))
    #define C_DMA_CPC_REG(d_channel_index)            * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CPC_OFFSET(d_channel_index))
  
  
  
    /*
     *  DMA_GCR register definition
     */
    /* Bits position in the register */
    #define C_DMA_GCR_FREE_POS                        2
    #define C_DMA_GCR_AUTO_GATE_POS                   3
    
    /* Mask of the field in the register */
    #define C_DMA_GCR_FREE_MASK                       0x0001
    #define C_DMA_GCR_AUTO_GATE_MASK                  0x0001
  
   
   
    /*
     *  DMA_AR register definition
     */
    /* Bits position in the register */
    #define C_DMA_AR_IMIF_PRIO_POS                    0
    #define C_DMA_AR_RHEA_PRIO_POS                    3
    #define C_DMA_AR_API_PRIO_POS                     4
    
    /* Mask of the field in the register */
    #define C_DMA_AR_IMIF_PRIO_MASK                   0x0007
    #define C_DMA_AR_RHEA_PRIO_MASK                   0x0001
    #define C_DMA_AR_API_PRIO_MASK                    0x0001
    

    /*
     *  DMA_CSDP register definition
     */
    /* Bits position in the register */
    #define C_DMA_CSDP_DATA_TYPE_POS                  0
    #define C_DMA_CSDP_SRC_POS                        2
    #define C_DMA_CSDP_SRC_PACK_POS                   6
    #define C_DMA_CSDP_SRC_BURST_EN_POS               7
    #define C_DMA_CSDP_DST_POS                        9
    #define C_DMA_CSDP_DST_PACK_POS                   13
    #define C_DMA_CSDP_DST_BURST_EN_POS               14
    
    /* Mask of the field in the register */
    #define C_DMA_CSDP_DATA_TYPE_MASK                 0x0003
    #define C_DMA_CSDP_SRC_MASK                       0x000F
    #define C_DMA_CSDP_SRC_PACK_MASK                  0x0001
    #define C_DMA_CSDP_SRC_BURST_EN_MASK              0x0003
    #define C_DMA_CSDP_DST_MASK                       0x000F
    #define C_DMA_CSDP_DST_PACK_MASK                  0x0001
    #define C_DMA_CSDP_DST_BURST_EN_MASK              0x0003


    /*
     *  DMA_CCR register definition
     */
    /* Bits position in the register */
    #define C_DMA_CCR_SYNC_POS                        0
    #define C_DMA_CCR_PRIO_POS                        6
    #define C_DMA_CCR_EN_POS                          7
    #define C_DMA_CCR_AUTO_INIT_POS                   8
    #define C_DMA_CCR_FIFO_FLUSH_POS                  10
    #define C_DMA_CCR_SRC_AMODE_POS                   12
    #define C_DMA_CCR_DST_AMODE_POS                   14
    
    /* Mask of the field in the register */
    #define C_DMA_CCR_SYNC_MASK                       0x001F
    #define C_DMA_CCR_PRIO_MASK                       0x0001
    #define C_DMA_CCR_EN_MASK                         0x0001
    #define C_DMA_CCR_AUTO_INIT_MASK                  0x0001
    #define C_DMA_CCR_FIFO_FLUSH_MASK                 0x0001
    #define C_DMA_CCR_SRC_AMODE_MASK                  0x0003
    #define C_DMA_CCR_DST_AMODE_MASK                  0x0003


    /*
     *  DMA_CICR register definition
     */
    /* Bits position in the register */
    #define C_DMA_CICR_TOUT_IE_POS                    0
    #define C_DMA_CICR_DROP_IE_POS                    1
    #define C_DMA_CICR_FRAME_IE_POS                   3
    #define C_DMA_CICR_BLOCK_IE_POS                   5
    #define C_DMA_CICR_HALF_BLOCK_IE_POS              6
    
    /* Mask of the field in the register */
    #define C_DMA_CICR_TOUT_IE_MASK                   0x0001
    #define C_DMA_CICR_DROP_IE_MASK                   0x0001
    #define C_DMA_CICR_FRAME_IE_MASK                  0x0001
    #define C_DMA_CICR_BLOCK_IE_MASK                  0x0001
    #define C_DMA_CICR_HALF_BLOCK_IE_MASK             0x0001


    /*
     *  DMA_CSR register definition
     */
    /* Bits position in the register */
    #define C_DMA_CSR_TOUT_POS                        0
    #define C_DMA_CSR_DROP_POS                        1
    #define C_DMA_CSR_FRAME_POS                       3
    #define C_DMA_CSR_BLOCK_POS                       5
    #define C_DMA_CSR_SYNC_POS                        6
    #define C_DMA_CSR_HALF_BLOCK_POS                  7
    #define C_DMA_CSR_TOUT_SRC_NDST_POS                8
    
    /* Mask of the field in the register */
    #define C_DMA_CSR_TOUT_MASK                       0x0001
    #define C_DMA_CSR_DROP_MASK                       0x0001
    #define C_DMA_CSR_FRAME_MASK                      0x0001
    #define C_DMA_CSR_BLOCK_MASK                      0x0001
    #define C_DMA_CSR_SYNC_MASK                       0x0001
    #define C_DMA_CSR_HALF_BLOCK_MASK                 0x0001
    #define C_DMA_CSR_TOUT_SRC_NDST_MASK              0x0001



    /****************************************************************************
     *                            TYPE DEFINITION
     ***************************************************************************/

    /*
    *  Channel number definition
    */
    typedef  SYS_UWORD8  T_DMA_TYPE_CHANNEL_NUMBER;
    #define   C_DMA_CHANNEL_0      0
    #define   C_DMA_CHANNEL_1      1
    #define   C_DMA_CHANNEL_2      2
    #define   C_DMA_CHANNEL_3      3
    #define   C_DMA_CHANNEL_4      4
    #define   C_DMA_CHANNEL_5      5



    #define   C_DMA_CHANNEL_0_MASK              0x01
    #define   C_DMA_CHANNEL_1_MASK              0x02
    #define   C_DMA_CHANNEL_2_MASK              0x04
    #define   C_DMA_CHANNEL_3_MASK              0x08
    #define   C_DMA_CHANNEL_4_MASK              0x10
    #define   C_DMA_CHANNEL_5_MASK              0x20


    /*
    *  Channel secure parameter definition
    */
    /*  channel secured, must be used with crypto module  */

    typedef  SYS_UWORD8  T_DMA_TYPE_CHANNEL_SECURED;
    #define    C_DMA_CHANNEL_NOT_SECURED    0    
    #define    C_DMA_CHANNEL_SECURED        1    

    /*
    *  Channel data type definition
    */

    typedef SYS_UWORD8  T_DMA_TYPE_CHANNEL_DATA_TYPE;
    #define    C_DMA_DATA_S8      0        /* byte definition */
    #define    C_DMA_DATA_S16     1        /* half word definition */
    #define    C_DMA_DATA_S32      2        /* word definition */



    /*
    *  Port definition
    */


    typedef SYS_UWORD8      T_DMA_TYPE_CHANNEL_PORT;    
    #define    C_DMA_IMIF_PORT      0        /*  IMIF PORT definition */
    #define    C_DMA_RHEA_PORT      1        /*  RHEA PORT definition */
    #define    C_DMA_API_PORT       2        /*  API PORT definition  */



    /*
    *  port packing definition
    */
    /*   port is performing packing to increase bandwidth if possible */

    typedef SYS_UWORD8  T_DMA_TYPE_CHANNEL_PACKED;
    #define    C_DMA_CHANNEL_NOT_PACKED  0      
    #define    C_DMA_CHANNEL_PACKED      1      


    /*
    *  port transfer busrt/single definition
    */


    typedef SYS_UWORD8  T_DMA_TYPE_CHANNEL_BURST_EN;
    #define    C_DMA_CHANNEL_SINGLE    0      /*  port transfer Single */
    #define    C_DMA_CHANNEL_BURST4    2      /*  port transfer burst 4 bytes, only IMIF can manage it */
  

    /*
    *  Channel synchronisation definition
    */

    typedef SYS_UWORD8  T_DMA_TYPE_CHANNEL_HW_SYNCH;
    #define    C_DMA_CHANNEL_NO_SYNCH        0      /*  No Synch means software synchronisation */
    #define    C_DMA_CHANNEL_RIF_TX          1
    #define    C_DMA_CHANNEL_RIF_RX          2
    #define    C_DMA_CHANNEL_LCD              3
    #define    C_DMA_CHANNEL_UART_MODEM1_TX  4