fir_top.cdb.qmsg

来自「《ALTERA FPGACPLD高级篇》LogicLock设计实例」· QMSG 代码 · 共 7 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Compiler Database Interface " "Info: Running Quartus II Compiler Database Interface" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 187 1/20/2004 SJ Full Version " "Info: Version 4.0 Build 187 1/20/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 19 13:09:41 2004 " "Info: Processing started: Thu Feb 19 13:09:41 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb fir_top -c fir_top --vqm=c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/atom_netlists/fir_top.vqm " "Info: Command: quartus_cdb fir_top -c fir_top --vqm=c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/atom_netlists/fir_top.vqm" {  } {  } 0}
{ "Info" "IBASEO_GENERATE_LOGICLOCK_FILES_FOR_POSTFIT_NETLIST" "" "Info: VQM is being generated using the Post-Fitter Netlist." {  } {  } 0}
{ "Info" "IQATM_GENERATED_VQM_FILE" "c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/atom_netlists/fir_top.vqm " "Info: Generated Verilog Quartus Mapping File c:/developing_classes/acc_quartusii/sd_edits/adv_qii4_0_test2/logiclock/fir/atom_netlists/fir_top.vqm" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Compiler Database Interface 0 s 0 s " "Info: Quartus II Compiler Database Interface was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 19 13:09:52 2004 " "Info: Processing ended: Thu Feb 19 13:09:52 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0}  } {  } 0}