fir_top.fit.eqn

《ALTERA FPGACPLD高级篇》LogicLock设计实例

F1_a_reg[14] = AMPP_FUNCTION(clock, C3L15Q, VCC, GND);


--F1_rst_dly is fir_top_st:fir_top_st_component|scale_accum:Usa|rst_dly at LC_X13_Y3_N9
--operation mode is normal

F1_rst_dly = AMPP_FUNCTION(clock, G1_tdl_wait[6], VCC);


--F1_a_reg[13] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[13] at LC_X13_Y3_N8
--operation mode is normal

F1_a_reg[13] = AMPP_FUNCTION(clock, C3L74Q, VCC);


--F1_a_reg[12] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[12] at LC_X13_Y2_N1
--operation mode is normal

F1_a_reg[12] = AMPP_FUNCTION(clock, C3L34Q, VCC);


--F1_a_reg[11] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[11] at LC_X8_Y3_N2
--operation mode is normal

F1_a_reg[11] = AMPP_FUNCTION(clock, C3L14Q, VCC);


--F1_a_reg[10] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[10] at LC_X12_Y3_N9
--operation mode is normal

F1_a_reg[10] = AMPP_FUNCTION(clock, C3L73Q, VCC);


--F1_a_reg[9] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[9] at LC_X14_Y3_N9
--operation mode is normal

F1_a_reg[9] = AMPP_FUNCTION(clock, C3L33Q, VCC, GND);


--F1_a_reg[8] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[8] at LC_X12_Y4_N1
--operation mode is normal

F1_a_reg[8] = AMPP_FUNCTION(clock, C3L92Q, VCC);


--F1_a_reg[7] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[7] at LC_X12_Y3_N8
--operation mode is normal

F1_a_reg[7] = AMPP_FUNCTION(clock, C3L52Q, VCC, GND);


--F1_a_reg[6] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[6] at LC_X13_Y5_N5
--operation mode is normal

F1_a_reg[6] = AMPP_FUNCTION(clock, C3L32Q, VCC);


--F1_a_reg[5] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[5] at LC_X13_Y4_N1
--operation mode is normal

F1_a_reg[5] = AMPP_FUNCTION(clock, C3L91Q, VCC);


--F1_a_reg[4] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[4] at LC_X14_Y4_N1
--operation mode is normal

F1_a_reg[4] = AMPP_FUNCTION(clock, C3L51Q, VCC);


--F1_a_reg[3] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[3] at LC_X14_Y4_N0
--operation mode is normal

F1_a_reg[3] = AMPP_FUNCTION(clock, C3L11Q, VCC);


--F1_a_reg[2] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[2] at LC_X13_Y2_N0
--operation mode is normal

F1_a_reg[2] = AMPP_FUNCTION(clock, C3L7Q, VCC, GND);


--F1_a_reg[1] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[1] at LC_X13_Y2_N2
--operation mode is normal

F1_a_reg[1] = AMPP_FUNCTION(clock, C3L5Q, VCC);


--F1_a_reg[0] is fir_top_st:fir_top_st_component|scale_accum:Usa|a_reg[0] at LC_X12_Y3_N1
--operation mode is normal

F1_a_reg[0] = AMPP_FUNCTION(clock, C3L1Q, VCC, GND);


--G1_tdl_wait[0] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[0] at LC_X12_Y4_N7
--operation mode is normal

G1_tdl_wait[0] = AMPP_FUNCTION(clock, G1_tdl_wait[1], !rst, GND);


--G1L1 is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~83 at LC_X12_Y3_N0
--operation mode is normal

G1L1 = AMPP_FUNCTION(G1_tdl_wait[5], G1_tdl_wait[12], G1_tdl_wait[6]);

--G1_tdl_wait[11] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[11] at LC_X12_Y3_N0
--operation mode is normal

G1_tdl_wait[11] = AMPP_FUNCTION(clock, G1_tdl_wait[12], !rst, GND);


--G1_tdl_wait[8] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[8] at LC_X12_Y3_N7
--operation mode is normal

G1_tdl_wait[8] = AMPP_FUNCTION(clock, G1_tdl_wait[9], !rst);


--G1_tdl_wait[9] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[9] at LC_X12_Y4_N2
--operation mode is normal

G1_tdl_wait[9] = AMPP_FUNCTION(clock, G1_tdl_wait[10], !rst);


--G1_tdl_wait[10] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[10] at LC_X12_Y4_N9
--operation mode is normal

G1_tdl_wait[10] = AMPP_FUNCTION(clock, G1_tdl_wait[11], !rst, GND);


--G1L2 is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~84 at LC_X12_Y3_N5
--operation mode is normal

G1L2 = AMPP_FUNCTION(G1_tdl_wait[8], G1_tdl_wait[10], G1_tdl_wait[9]);

--G1_tdl_wait[7] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[7] at LC_X12_Y3_N5
--operation mode is normal

G1_tdl_wait[7] = AMPP_FUNCTION(clock, G1_tdl_wait[8], !rst, GND);


--G1_tdl_wait[3] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[3] at LC_X8_Y3_N7
--operation mode is normal

G1_tdl_wait[3] = AMPP_FUNCTION(clock, G1_tdl_wait[4], !rst);


--G1_tdl_wait[4] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[4] at LC_X8_Y3_N4
--operation mode is normal

G1_tdl_wait[4] = AMPP_FUNCTION(clock, G1_tdl_wait[5], !rst);


--G1_tdl_wait[1] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[1] at LC_X8_Y3_N1
--operation mode is normal

G1_tdl_wait[1] = AMPP_FUNCTION(clock, G1_tdl_wait[2], !rst, GND);


--G1L3 is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|i~85 at LC_X8_Y3_N3
--operation mode is normal

G1L3 = AMPP_FUNCTION(G1_tdl_wait[3], G1_tdl_wait[1], G1_tdl_wait[4]);

--G1_tdl_wait[2] is fir_top_st:fir_top_st_component|ser_ctrl_nc:Usc|tdl_wait[2] at LC_X8_Y3_N3
--operation mode is normal

G1_tdl_wait[2] = AMPP_FUNCTION(clock, G1_tdl_wait[3], !rst, GND);


--C2L21Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[12]~reg0 at LC_X14_Y1_N8
--operation mode is normal

C2L21Q = AMPP_FUNCTION(clock, S1_q_b[11], VCC);


--C2L11Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[10]~reg0 at LC_X12_Y1_N8
--operation mode is normal

C2L11Q = AMPP_FUNCTION(clock, S1_q_b[10], VCC, GND);


--C2L01Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[9]~reg0 at LC_X12_Y1_N1
--operation mode is normal

C2L01Q = AMPP_FUNCTION(clock, S1_q_b[9], VCC, GND);


--C2L9Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[8]~reg0 at LC_X7_Y1_N7
--operation mode is normal

C2L9Q = AMPP_FUNCTION(clock, S1_q_b[8], VCC, GND);


--C2L8Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[7]~reg0 at LC_X12_Y1_N7
--operation mode is normal

C2L8Q = AMPP_FUNCTION(clock, S1_q_b[7], VCC, GND);


--C2L7Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[6]~reg0 at LC_X12_Y1_N2
--operation mode is normal

C2L7Q = AMPP_FUNCTION(clock, S1_q_b[6], VCC, GND);


--C2L6Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[5]~reg0 at LC_X14_Y2_N1
--operation mode is normal

C2L6Q = AMPP_FUNCTION(clock, S1_q_b[5], VCC);


--C2L5Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[4]~reg0 at LC_X12_Y4_N6
--operation mode is normal

C2L5Q = AMPP_FUNCTION(clock, S1_q_b[4], VCC, GND);


--C2L4Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[3]~reg0 at LC_X12_Y2_N7
--operation mode is normal

C2L4Q = AMPP_FUNCTION(clock, S1_q_b[3], VCC, GND);


--C2L3Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[2]~reg0 at LC_X12_Y2_N2
--operation mode is normal

C2L3Q = AMPP_FUNCTION(clock, S1_q_b[2], VCC, GND);


--C2L2Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[1]~reg0 at LC_X12_Y2_N8
--operation mode is normal

C2L2Q = AMPP_FUNCTION(clock, S1_q_b[1], VCC, GND);


--C2L1Q is fir_top_st:fir_top_st_component|sadd:Uaddl_0_n_1_n|res[0]~reg0 at LC_X14_Y2_N2
--operation mode is normal

C2L1Q = AMPP_FUNCTION(clock, S1_q_b[0], VCC);


--M71L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_16_n|data_out[0]~reg0 at LC_X8_Y3_N6
--operation mode is normal

M71L2Q = AMPP_FUNCTION(clock, L2_sft03_n[0], L1_sft15_n[0], M71_c_out, VCC);


--M81L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_17_n|data_out[0]~reg0 at LC_X7_Y5_N0
--operation mode is normal

M81L2Q = AMPP_FUNCTION(clock, L2_sft00_n[0], L2_sft02_n[0], M81_c_out, VCC);


--M91L1Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_18_n|data_out[0]~reg0 at LC_X13_Y5_N0
--operation mode is normal

M91L1Q = AMPP_FUNCTION(clock, L2_sft01_n[0], VCC, GND);


--M9L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_8_n|data_out[0]~reg0 at LC_X5_Y5_N0
--operation mode is normal

M9L2Q = AMPP_FUNCTION(clock, L2_sft11_n[0], L1_sft07_n[0], M9_c_out, VCC);


--M01L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_9_n|data_out[0]~reg0 at LC_X3_Y4_N2
--operation mode is normal

M01L2Q = AMPP_FUNCTION(clock, L2_sft10_n[0], L1_sft08_n[0], M01_c_out, VCC);


--M11L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_10_n|data_out[0]~reg0 at LC_X7_Y4_N0
--operation mode is normal

M11L2Q = AMPP_FUNCTION(clock, L1_sft09_n[0], L2_sft09_n[0], M11_c_out, VCC);


--M21L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_11_n|data_out[0]~reg0 at LC_X6_Y3_N6
--operation mode is normal

M21L2Q = AMPP_FUNCTION(clock, L2_sft08_n[0], L1_sft10_n[0], M21_c_out, VCC);


--M31L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_12_n|data_out[0]~reg0 at LC_X5_Y2_N8
--operation mode is normal

M31L2Q = AMPP_FUNCTION(clock, L2_sft07_n[0], L1_sft11_n[0], M31_c_out, VCC);


--M41L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_13_n|data_out[0]~reg0 at LC_X7_Y6_N2
--operation mode is normal

M41L2Q = AMPP_FUNCTION(clock, L2_sft06_n[0], L1_sft12_n[0], M41_c_out, VCC);


--M51L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_14_n|data_out[0]~reg0 at LC_X9_Y2_N0
--operation mode is normal

M51L2Q = AMPP_FUNCTION(clock, L2_sft05_n[0], L1_sft13_n[0], M51_c_out, VCC);


--M61L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_15_n|data_out[0]~reg0 at LC_X8_Y1_N5
--operation mode is normal

M61L2Q = AMPP_FUNCTION(clock, L2_sft04_n[0], L1_sft14_n[0], M61_c_out, VCC);


--M1L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_0_n|data_out[0]~reg0 at LC_X8_Y2_N4
--operation mode is normal

M1L2Q = AMPP_FUNCTION(clock, K1_add_dly2[1], L3_sft03_n[0], M1_c_out, VCC);


--M2L2Q is fir_top_st:fir_top_st_component|sym_add_ser:sym_1_n|data_out[0]~reg0 at LC_X7_Y3_N0
--operation