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📄 fir_top_rpt.htm

📁 《ALTERA FPGACPLD高级篇》LogicLock设计实例
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<H3>FIR Compiler MegaWizard Report File</H2>
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<H3>General Info</H3>
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<TR BGCOLOR="#FFFFFF"><TD>version </TD><TD> 2.7.0</TD></TR>

<TR BGCOLOR="#FFFFFF"><TD>Architecture </TD><TD> Serial</TD>
<TR BGCOLOR="#FFFFFF"><TD>clock cycles required for computation </TD><TD> 12</TD></TR>
<TR BGCOLOR="#FFFFFF"><TD># of Clocks To Hold Input Data </TD><TD> 13 </TD></TR>
<TR BGCOLOR="#FFFFFF"><TD># of Clocks Output Data is held for </TD><TD>13</TD></TR>
<TR BGCOLOR="#FFFFFF"><TD>Input Bit Width </TD><TD> 12</TD></TR>
<TR BGCOLOR="#FFFFFF"><TD>Coeficient Bit Width </TD><TD>10</TD></TR>
<TR BGCOLOR="#FFFFFF"  valign="top"><TD><b>pipeline level </TD><TD>1</TD></TR>
<TR BGCOLOR="#FFFFFF"  valign="top"><TD><b>pipeline delay </TD><TD>18 clocks</TD></TR>
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<H3>Synthesis / Simulation Files</H3>
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<CAPTION ALIGN="LEFT">Quartus II</CAPTION><TR BGCOLOR="#FFFFFF"><TD>top level Quartus II synthesis file</TD><TD>fir_top.tdf</TD> </TR>

<TR BGCOLOR="#FFFFFF"><TD>Quartus II Synthesis Files<BR><BR></TD><TD>fir_top_st.v<br>fir_top.tdf</TD> </TR>
<TR BGCOLOR="#FFFFFF"><TD>Quartus II Testbed File </TD><TD>fir_top.vec</TD> </TR>
<TR BGCOLOR="#FFFFFF"><TD>Quartus Memory Initializtion Files</TD><TD></TD> </TR>
<TR BGCOLOR="#FFFFFF"><TD>Entity Settings Files(.esf) for Quartus II Synthesis </TD><TD>lc_tdl_mr.esf<br>lc_tdl_en.esf<br>lc_tdl.esf<br>lc_tdl_strat.esf<br>tdl_da_lc.esf<br>sadd.esf<br>sadd_lpm.esf<br></TD> </TR>
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<CAPTION ALIGN="LEFT">Verilog Simulation</CAPTION><TR BGCOLOR="#FFFFFF"><TD>top level Verilog simulation file </TD><TD>fir_top_sim.v </TD></TR><TR BGCOLOR="#FFFFFF"><TD>Verilog Simulation Files<BR><BR></TD><TD>fir_top_st_model.v<br>fir_top_sim.v<TR BGCOLOR="#FFFFFF"><TD>Verilog Memory Initializtion Files<br> (NOT COMPILLABLE) </TD><TD></TD> </TR>
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<CAPTION ALIGN="LEFT"> VHDL Simulation</CAPTION><TR BGCOLOR="#FFFFFF"><TD>top level VHDL simulation file </TD><TD>fir_top_sim.vhd</TD> </TR>
<TR BGCOLOR="#FFFFFF"><TD>VHDL Simulation Files <BR><BR></TD><TD>fir_top_st_model.vhd<br>fir_top_sim.vhd<br><TR BGCOLOR="#FFFFFF"><TD>VHDL Memory Initializtion Files<br> (NOT COMPILLABLE) </TD><TD></TD></TR>
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<CAPTION ALIGN="LEFT">MATLAB Model</CAPTION><TR BGCOLOR="#FFFFFF"><TD>MATLAB Test Bench </TD><TD>fir_top_tb.m </TD></TR><TR BGCOLOR="#FFFFFF"><TD>MATLAB Model Files<BR><BR></TD><TD>fir_top_mlab.m<br></TD> </TR>
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