fir_top_coef_lst_i.txt

来自「《ALTERA FPGACPLD高级篇》LogicLock设计实例」· 文本 代码 · 共 38 行

363	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
377	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
391	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
405	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
418	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
430	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
441	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
452	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
461	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
471	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
479	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
486	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
493	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
497	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
502	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
506	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
508	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
510	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
511	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
510	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
508	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
506	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
502	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
497	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
493	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
486	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
479	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
471	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
461	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
452	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
441	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
430	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
418	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
405	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
391	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
377	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	
363	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0