diff_io_top.map.rpt

《ALTERA FPGACPLD高级篇》高速串行差分接口（HSDI）设计实例

+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/examples/Examples-10-2/Verilog/Diff_io_top.map.eqn.


+---------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                      ;
+---------------------------------------------------------------------------+-----------------+
; File Name                                                                 ; Used in Netlist ;
+---------------------------------------------------------------------------+-----------------+
; E:/examples/Examples-10-2/Verilog/Diff_io_top.v                           ; yes             ;
; E:/examples/Examples-10-2/Verilog/lvds_rx.v                               ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf                ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/apex20ke_lvds_receiver.inc    ; yes             ;
; E:/examples/Examples-10-2/Verilog/mult.v                                  ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf               ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/stratix_mac_mult.inc          ; yes             ;
; E:/examples/Examples-10-2/Verilog/db/mult_add_v4n1.tdf                    ; yes             ;
; E:/examples/Examples-10-2/Verilog/lvds_tx.v                               ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf                ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/apex20ke_lvds_transmitter.inc ; yes             ;
+---------------------------------------------------------------------------+-----------------+


+--------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                ;
+---------------------------------+----------------------------------------------------------+
; Resource                        ; Usage                                                    ;
+---------------------------------+----------------------------------------------------------+
; Logic cells                     ; 32                                                       ;
; Total combinational functions   ; 0                                                        ;
; Total 4-input functions         ; 0                                                        ;
; Total 3-input functions         ; 0                                                        ;
; Total 2-input functions         ; 0                                                        ;
; Total 1-input functions         ; 0                                                        ;
; Total 0-input functions         ; 0                                                        ;
; Combinational cells for routing ; 0                                                        ;
; Total registers                 ; 32                                                       ;
; I/O pins                        ; 8                                                        ;
; DSP block 9-bit elements        ; 1                                                        ;
; Total PLLs                      ; 2                                                        ;
; SERDES transmitters             ; 3                                                        ;
; SERDES receivers                ; 2                                                        ;
; Maximum fan-out node            ; lvds_rx:lvds_rx_inst|altlvds_rx:altlvds_rx_component|pll ;
; Maximum fan-out                 ; 37                                                       ;
; Total fan-out                   ; 112                                                      ;
; Average fan-out                 ; 2.29                                                     ;
+---------------------------------+----------------------------------------------------------+


+------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary   ;
+----------------------------------+-------------+
; Statistic                        ; Number Used ;
+----------------------------------+-------------+
; Simple Multipliers (9-bit)       ; 1           ;
; Simple Multipliers (18-bit)      ; 0           ;
; Simple Multipliers (36-bit)      ; 0           ;
; Multiply Accumulators (18-bit)   ; 0           ;
; Two-Multipliers Adders (9-bit)   ; 0           ;
; Two-Multipliers Adders (18-bit)  ; 0           ;
; Four-Multipliers Adders (9-bit)  ; 0           ;
; Four-Multipliers Adders (18-bit) ; 0           ;
; DSP Blocks                       ; 0           ;
; DSP Block 9-bit Elements         ; 1           ;
+----------------------------------+-------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 32    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 0     ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 32    ;
; Number of cells with combinational logic only          ; 0     ;
; Number of cells with registers only                    ; 32    ;
; Number of cells with combinational logic and registers ; 0     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version
    Info: Processing started: Mon Sep 13 22:26:53 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Diff_io_top -c Diff_io_top
Info: Used source file sld_hub.vhd for a SignalTap II or debug node instance
Warning: Can't analyze file -- file E:/examples/Examples-10-2/Verilog/sld_hub.vhd is missing
Info: Using design file Diff_io_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: Diff_io_top
Info: Using design file lvds_rx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lvds_rx
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altlvds_rx.tdf
    Info: Found entity 1: altlvds_rx
Info: Using design file mult.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: mult
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altmult_add.tdf
    Info: Found entity 1: altmult_add
Info: Found 1 design units, including 1 entities, in source file db/mult_add_v4n1.tdf
    Info: Found entity 1: mult_add_v4n1
Info: Using design file lvds_tx.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lvds_tx
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altlvds_tx.tdf
    Info: Found entity 1: altlvds_tx
Info: Implemented 48 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 4 output pins
    Info: Implemented 32 logic cells
    Info: Implemented 2 ClockLock PLLs
    Info: Implemented 1 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Sep 13 22:26:55 2004
    Info: Elapsed time: 00:00:01