lvds_tx_bb.v

《ALTERA FPGACPLD高级篇》高速串行差分接口（HSDI）设计实例

// megafunction wizard: %ALTLVDS%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_tx 

// ============================================================
// File Name: lvds_tx.v
// Megafunction Name(s):
// 			altlvds_tx
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version
// ************************************************************

//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.

module lvds_tx (
	tx_in,
	tx_inclock,
	tx_out,
	tx_outclock);

	input	[15:0]  tx_in;
	input	  tx_inclock;
	output	[1:0]  tx_out;
	output	  tx_outclock;

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Int_Device STRING "Stratix"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "2"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "8"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Outclock_Divide_By NUMERIC "8"
// Retrieval info: PRIVATE: Output_Clock_alignment STRING "EDGE_ALIGNED"
// Retrieval info: PRIVATE: PLL_Freq STRING "105.00"
// Retrieval info: PRIVATE: PLL_Period STRING "9.523"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "840"
// Retrieval info: PRIVATE: Input_Clock_alignment STRING "EDGE_ALIGNED"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: PRIVATE: Use_CoreClock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_Choices STRING "TX_CLKIN"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "2"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "8"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
// Retrieval info: CONSTANT: OUTCLOCK_DIVIDE_BY NUMERIC "8"
// Retrieval info: CONSTANT: OUTCLOCK_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "9523"
// Retrieval info: CONSTANT: OUTPUT_DATA_RATE NUMERIC "840"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: USED_PORT: tx_in 0 0 16 0 INPUT NODEFVAL tx_in[15..0]
// Retrieval info: USED_PORT: tx_out 0 0 2 0 OUTPUT NODEFVAL tx_out[1..0]
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT GND tx_inclock
// Retrieval info: USED_PORT: tx_outclock 0 0 0 0 OUTPUT NODEFVAL tx_outclock
// Retrieval info: CONNECT: @tx_in 0 0 16 0 tx_in 0 0 16 0
// Retrieval info: CONNECT: tx_out 0 0 2 0 @tx_out 0 0 2 0
// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
// Retrieval info: CONNECT: tx_outclock 0 0 0 0 @tx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lvds_tx_bb.v TRUE