lvds_rx.bsf

《ALTERA FPGACPLD高级篇》高速串行差分接口（HSDI）设计实例

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 0 0 288 160)
	(text "lvds_rx" (rect 124 1 171 17)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 144 25 156)(font "Arial" ))
	(port
		(pt 0 32)
		(input)
		(text "rx_in[1..0]" (rect 0 0 56 14)(font "Arial" (font_size 8)))
		(text "rx_in[1..0]" (rect 4 19 51 32)(font "Arial" (font_size 8)))
		(line (pt 0 32)(pt 72 32)(line_width 3))
	)
	(port
		(pt 0 48)
		(input)
		(text "rx_inclock" (rect 0 0 57 14)(font "Arial" (font_size 8)))
		(text "rx_inclock" (rect 4 35 50 48)(font "Arial" (font_size 8)))
		(line (pt 0 48)(pt 72 48)(line_width 1))
	)
	(port
		(pt 0 64)
		(input)
		(text "rx_data_align" (rect 0 0 76 14)(font "Arial" (font_size 8)))
		(text "rx_data_align" (rect 4 51 69 64)(font "Arial" (font_size 8)))
		(line (pt 0 64)(pt 72 64)(line_width 1))
	)
	(port
		(pt 288 32)
		(output)
		(text "rx_out[15..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
		(text "rx_out[15..0]" (rect 224 19 283 32)(font "Arial" (font_size 8)))
		(line (pt 288 32)(pt 216 32)(line_width 3))
	)
	(port
		(pt 288 48)
		(output)
		(text "rx_outclock" (rect 0 0 66 14)(font "Arial" (font_size 8)))
		(text "rx_outclock" (rect 229 35 281 48)(font "Arial" (font_size 8)))
		(line (pt 288 48)(pt 192 48)(line_width 1))
	)
	(port
		(pt 288 64)
		(output)
		(text "rx_locked" (rect 0 0 55 14)(font "Arial" (font_size 8)))
		(text "rx_locked" (rect 238 51 282 64)(font "Arial" (font_size 8)))
		(line (pt 288 64)(pt 192 64)(line_width 1))
	)
	(drawing
		(text "LVDS Receiver" (rect 100 38 165 50)(font "Arial" ))
		(text "2 channels, x8" (rect 102 54 163 66)(font "Arial" ))
		(text "105.00 MHz" (rect 108 70 157 82)(font "Arial" ))
		(text "I/P data rate=840.00" (rect 90 86 175 98)(font "Arial" ))
		(text "Outclk Freq = 105.00" (rect 88 102 176 114)(font "Arial" ))
		(text "Stratix" (rect 253 146 280 158)(font "Arial" ))
		(line (pt 72 24)(pt 192 24)(line_width 1))
		(line (pt 192 24)(pt 192 128)(line_width 1))
		(line (pt 192 128)(pt 72 128)(line_width 1))
		(line (pt 72 128)(pt 72 24)(line_width 1))
		(line (pt 72 44)(pt 77 49)(line_width 1))
		(line (pt 72 52)(pt 77 47)(line_width 1))
		(line (pt 208 27)(pt 216 27)(line_width 1))
		(line (pt 216 27)(pt 216 39)(line_width 1))
		(line (pt 216 39)(pt 208 39)(line_width 1))
		(line (pt 208 39)(pt 208 27)(line_width 1))
		(line (pt 208 34)(pt 210 36)(line_width 1))
		(line (pt 210 36)(pt 208 38)(line_width 1))
		(line (pt 200 36)(pt 208 36)(line_width 1))
		(line (pt 192 32)(pt 208 32)(line_width 3))
		(line (pt 200 48)(pt 200 36)(line_width 1))
	)
)