diff_io_top.fit.rpt

《ALTERA FPGACPLD高级篇》高速串行差分接口（HSDI）设计实例

Fitter report for Diff_io_top
Mon Sep 13 22:27:17 2004
Version 4.1 Build 207 08/26/2004 Service Pack 1.04 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Floorplan View
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. PLL Summary
 14. PLL Usage
 15. Differential I/O Receiver
 16. Differential I/O Transmitter
 17. Output Pin Load For Reported TCO
 18. Fitter Resource Utilization by Entity
 19. Delay Chain Summary
 20. Pad To Core Delay Chain Fanout
 21. Control Signals
 22. Global & Other Fast Signals
 23. Non-Global High Fan-Out Signals
 24. Fitter DSP Block Usage Summary
 25. DSP Block Details
 26. Interconnect Usage Summary
 27. LAB Logic Elements
 28. LAB-wide Signals
 29. LAB Signals Sourced
 30. LAB Signals Sourced Out
 31. LAB Distinct Inputs
 32. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+-----------------------------------------------------------------------------+
; Fitter Summary                                                              ;
+--------------------------+--------------------------------------------------+
; Fitter Status            ; Successful - Mon Sep 13 22:27:17 2004            ;
; Quartus II Version       ; 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version ;
; Revision Name            ; Diff_io_top                                      ;
; Top-level Entity Name    ; Diff_io_top                                      ;
; Family                   ; Stratix                                          ;
; Device                   ; EP1S10F780C6                                     ;
; Timing Models            ; Production                                       ;
; Total logic elements     ; 32 / 10,570 ( < 1 % )                            ;
; Total pins               ; 14 / 427 ( 3 % )                                 ;
; Total memory bits        ; 0 / 920,448 ( 0 % )                              ;
; DSP block 9-bit elements ; 1 / 48 ( 2 % )                                   ;
; Total PLLs               ; 1 / 6 ( 16 % )                                   ;
; Total DLLs               ; 0 / 2 ( 0 % )                                    ;
+--------------------------+--------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                      ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option                                             ; Setting                        ; Default Value                  ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device                                             ; EP1S10F780C6                   ;                                ;
; Optimize Hold Timing                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Timing                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing         ; On                             ; On                             ;
; Limit to One Fitting Attempt                       ; Off                            ; Off                            ;
; Final Placement Optimizations                      ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                      ; 1                              ; 1                              ;
; Slow Slew Rate                                     ; Off                            ; Off                            ;
; PCI I/O                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                 ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix/Stratix GX        ; Auto                           ; Auto                           ;
; Auto Delay Chains                                  ; On                             ; On                             ;
; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion -- Logic Duplication          ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;