mult_inst.v

来自「《ALTERA FPGACPLD高级篇》高速串行差分接口（HSDI）设计实例」· Verilog 代码 · 共 7 行

mult	mult_inst (
	.clock0 ( clock0_sig ),
	.dataa_0 ( dataa_0_sig ),
	.datab_0 ( datab_0_sig ),
	.result ( result_sig )
	);