init.h
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H
381 行
typedef struct tagRegAdrVal
{
unsigned char ucRegAdr;
unsigned char ucRegVal;
}REGADRVAL;
#ifndef __INIT_H__
#define __INIT_H__
#include "AU_7_A.h"
#include "RESOLUTION.h"
#include "TW803_REGS.H"
unsigned char const ucaSignalStdRegP2[6]={
0x0c, 0x18, 0x19, 0x1a, 0x1b, 0x82
};
unsigned char const ucaSignalStdValP2[36]={
//NTSC
0x8a, 0x21, 0xf0, 0x7c, 0x0f, 0x42 ,
//NTSC 4 // Add by Sherman 06'01'26
0x8a, 0x2a, 0x09, 0x8a, 0xcb, 0x42 ,
//PAL_M // Add by Sherman 06'01'26
0x67, 0x21, 0xe6, 0xef, 0xa3, 0x52 ,
//PAL
0x67, 0x2a, 0x09, 0x8a, 0xcb, 0x52 ,
//PAL_CN // Add by Sherman 06'01'26
0x67, 0x21, 0xf6, 0x94, 0x46, 0x52 ,
//SECAM
0x80, 0x28, 0xb3, 0x3b, 0xb2, 0x52 ,
};
#define __OSD_ESTR__
/*
Source uiaSrcMux1[]={
{0x0000, NULL , NULL, NULL, NULL},
#ifdef TV
{0x0804, itypeTV, isrcVIDEO, NULL, iTV_E},
#endif
{0x0100, itypeCVBS, isrcVIDEO, NULL, iCVBS_1_E},
{0x1406, itypeSVIDEO, isrcVIDEO, NULL, iSVideo_E},
#ifdef PC_MODE
{0x2A24, itypeRGB, isrcANALOG, NULL, iVGA_E},
#endif
{0x0100, itypeRGB565, isrcANALOG, NULL, iRGB565_E},
#ifdef YPbPr
{0x2824, itypeYPBPR, isrcVIDEO, NULL, iCOMPONENT_E},
#endif
{0x2824, itype656, isrcDIGITAL, itypeCVBS, iCVBS_2_E},
{0x0000, itypeEND, NULL, NULL, NULL},
};
*/
REGADRVAL const stInitOUT_T[]={
#ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
0xC8 , DFDIV_40, //PLLDIV_F
0xC9 , DIDIV, //PLLDIV_I
#endif
//DSP Colck Polarity
0xC1 , 0xc8, //POUT_CTRL3_REG
//H&V Main Display Pixel Clock Setted
0xDC ,(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
//H&V Display Pixel Clock Setted
#ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
0xB4 ,(H_Size&0xFF), //H Width //DWHSZ_L_REG
0xB5 ,(H_Size>>8), //DWHSZ_H_REG
0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
0xB7 ,(V_Size>>8), //DWVSZ_H_REG
0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
0xff , 0x00// End of register settings, bruce, 2006/01/09
};
/****************************************************************************
* T10x Register No. and values for System and Tcon initial *
****************************************************************************/
//====== InitT10x Register No. and values
REGADRVAL const stInitT10xP0[]={
//adr , value
0x0A , 0x60, //ADC_ROFF // Change by Sherman 06'01'10
0x0B , 0x60, //ADC_GOFF // Change by Sherman 06'01'10
0x0C , 0x60, //ADC_BOFF // Change by Sherman 06'01'10
0x16 , 0xD3,
0x1A , 0x87, //ADC_AGC_SEL_REG
0xC2 , 0x12, //POUT_VSYNC_CTRL_REG
//for image quality
0x6C , 0x80, //OP_SAT_REG
0x60 , 0x00, //DCTI_BW_REG
0x61 , 0x88,//For char clear //LUMA_PKCTRL_REG
0x62 , 0x18,//For char clear //BP_PKCOEF_REG
0x63 , 0x0F,//For char clear //HP_PKCOEF_REG
0x64 , 0x04,//For char clear //60 //LP_PKCOEF_REG
0x66 , 0x88,//For color clear enable DCTI //DCTI_GAINCO_REG
0X1C , 0xF0, //BLANK_SYNCLV_REG
0x97 , 0x95, //CSC_YCOEF_REG
0x98 , 0xCC, //CSC_CrRCOEF_REG
0x0D , 0x28, //5 //ADC_GENCTRL_REG
0xE0 , 0xa9,//92, //PW_MGRCTRL_REG
0x11 , 0x05, //YPbPr_CLPCTRL_REG
0x17 , 0x4c, // kenny 20060627
//Source Select--S Video
0x18 , 0x00, //ASRC_MUX_REG
0x19 , 0x07, //YCbCr_SW_REG
//Enable CSC
0x91 , 0x00, //BTIN_PATTERN_REG
//DSP Clock
#ifdef SEQ_MODE // For sequential mode, bruce, 2006/01/09
0xCB , (CPH1_PH | PHASE_DIV),
0xCC , (CPH3_PH | CPH2_PH),
0xC8 , DFDIV_S,
0xC9 , DIDIV_S,
0xCA , DODIV_S,
#else
0xC8 , DFDIV_40, //PLLDIV_F
0xC9 , DIDIV, //PLLDIV_I
0xCA , DODIV, //PLLDIV_O
#endif
0xC0 , 0x81,
//DSP Colck Polarity
0xC1 , 0xc8, //POUT_CTRL3_REG
//H&V Main Display Pixel Clock Setted
0xDC ,0xe5,//(H_Size&0xFF),//H Size //HMDISP_SIZE_L_REG
0xDD ,(H_Size>>8), //HMDISP_SIZE_H_REG
0xDE ,(V_Size&0xFF),//V Size //20 //VMDISP_SIZE_L_REG
0xDF ,(V_Size>>8), //VMDISP_SIZE_H_REG
//H&V Display Pixel Clock Setted
#ifdef _160_234
0xcb , 0x66,
0xcc , 0x42,
0x79 , 0x0d,
#endif
0xB0 , DISP_DFLT_HDENS, //H Start //DWHS_L_REG
0xB1 ,(DISP_DFLT_HDENS>>8), //DWHS_H_REG
0xB2 , DISP_DFLT_VDENS, //V Start //DWVS_L_REG
0xB3 ,(DISP_DFLT_VDENS>>8), //25 //DWVS_H_REG
0xB4 ,0xe5,//(H_Size&0xFF), //H Width //DWHSZ_L_REG
0xB5 ,(H_Size>>8), //DWHSZ_H_REG
0xB6 ,(V_Size&0xFF), //DWVSZ_L_REG
0xB7 ,(V_Size>>8), //DWVSZ_H_REG
0xB8 , DISP_DFLT_HTOTAL, //H Total //30 //PH_TOT_L_REG
0xB9 ,(DISP_DFLT_HTOTAL>>8), //PH_TOT_H_REG
0xBA , DISP_DFLT_VTOTAL, //V Total //PV_TOT_L_REG
0xBB ,(DISP_DFLT_VTOTAL>>8), //PV_TOT_H_REG
0xBC , DISP_DFLT_HSWIDTH, //HSYNC Width //PH_PW_L_REG
0xBD ,(DISP_DFLT_HSWIDTH>>8), //35 //PH_PW_H_REG
0xBE , DISP_DFLT_VSWIDTH, //VSYNC Width //PV_PW_L_REG
0xBF ,(DISP_DFLT_VSWIDTH>>8), //PV_PW_H_REG
//Scaling
0x72 , 0x33, //H Scale //SC_HOR_H1
0x73 , 0x73, //SC_HOR_H2
0x74 , 0x00, //V Scale //40 //SC_VER_V1
0x75 , 0x40, //SC_VER_V2
//LineBuffer Prefill
0xe2 , 0x11,
0x84 , 0x00, //LINE_BUF_L_REG
0x85 , 0x10, //LINE_BUF_H_REG
0xE1 , 0xa0, //OPIN_CFG_REG
0x50 , 0x10, //45 //VSYNC_TIME_MEA_REG
0x37 , 0x40, //VSYNC_MISSCNT_REG
0x38 , 0x50, //HSYNC_MISSCNT_L_REG
0x39 , 0x10, //HSYNC_MISSCNT_H_REG
0x3A , 0x20, //VSYNC_DLT_REG
0x3B , 0x03, //HSYNC_DLT_REG
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