r8c2a.h

这是一个用Ｔ108加上瑞萨公司Ｒ8Ｃ2Ａ做的一个ＯＳＤ显示。希望能帮上大家。

#define		vca27		vca2_addr.bit.b7			/* Voltage detection 2 enable bit */

/*------------------------------------------------------
  Voltage monitor 1 circuit control register
------------------------------------------------------*/
union	byte_def	vw1c_addr;
#define		vw1c		vw1c_addr.byte

#define		vw1c0		vw1c_addr.bit.b0			/* Voltage monitor 1 interrupt / reset enable bit */
#define		vw1c1		vw1c_addr.bit.b1			/* Voltage monitor 1 digital filter disable mode select bit */
#define		vw1c2		vw1c_addr.bit.b2			/* Voltage change detection flag */
#define		vw1c3		vw1c_addr.bit.b3			/* Voltage detection 1 signal monitor flag */
#define		vw1f0		vw1c_addr.bit.b4			/* Sampling clock select bit */
#define		vw1f1		vw1c_addr.bit.b5			/* Sampling clock select bit */
#define		vw1c6		vw1c_addr.bit.b6			/* Voltage monitor 1 circuit mode select bit */
#define		vw1c7		vw1c_addr.bit.b7			/* Voltage monitor 1 interrupt / reset generation condition select bit */

/*------------------------------------------------------
  Voltage monitor 2 circuit control register
------------------------------------------------------*/
union	byte_def	vw2c_addr;
#define		vw2c		vw2c_addr.byte

#define		vw2c0		vw2c_addr.bit.b0			/* Voltage monitor 2 interrupt / reset enable bit */
#define		vw2c1		vw2c_addr.bit.b1			/* Voltage monitor 2 digital filter disabled mode select bit */
#define		vw2c2		vw2c_addr.bit.b2			/* Voltage change detection flag */
#define		vw2c3		vw2c_addr.bit.b3			/* WDT Detection Flag */
#define		vw2f0		vw2c_addr.bit.b4			/* Sampling clock select bit */
#define		vw2f1		vw2c_addr.bit.b5			/* Sampling clock select bit */
#define		vw2c6		vw2c_addr.bit.b6			/* Voltage monitor 2 circuit mode select bit */
#define		vw2c7		vw2c_addr.bit.b7			/* Voltage monitor 2 interrupt / reset generation condition select bit */

/*------------------------------------------------------
  Voltage monitor 0 circuit control register
------------------------------------------------------*/
union	byte_def	vw0c_addr;
#define		vw0c		vw0c_addr.byte

#define		vw0c0		vw0c_addr.bit.b0			/* Voltage monitor 0 reset enable bit */
#define		vw0c1		vw0c_addr.bit.b1			/* Voltage monitor 0 digital filter disabled mode select bit */
#define		vw0c2		vw0c_addr.bit.b2			/*  */
#define		vw0f0		vw0c_addr.bit.b4			/* Sampling clock select bit */
#define		vw0f1		vw0c_addr.bit.b5			/* Sampling clock select bit */
#define		vw0c6		vw0c_addr.bit.b6			/* Voltage monitor 0 circuit mode select bit */
#define		vw0c7		vw0c_addr.bit.b7			/* Voltage monitor 0 reset generation condition select bit */

/*------------------------------------------------------
  UART0 bit rate register
------------------------------------------------------*/
union	byte_def	u0brg_addr;
#define		u0brg		u0brg_addr.byte

/*------------------------------------------------------
  UART1 bit rate register
------------------------------------------------------*/
union	byte_def	u1brg_addr;
#define		u1brg		u1brg_addr.byte

/*------------------------------------------------------
  UART2 bit rate register
------------------------------------------------------*/
union	byte_def	u2brg_addr;
#define		u2brg		u2brg_addr.byte

/*------------------------------------------------------
  SS control register H
------------------------------------------------------*/
union	byte_def	sscrh_addr;
#define		sscrh		sscrh_addr.byte

#define		cks0_sscrh	sscrh_addr.bit.b0			/* Transfer clock rate select bit */
#define		cks1_sscrh	sscrh_addr.bit.b1			/* Transfer clock rate select bit */
#define		cks2_sscrh	sscrh_addr.bit.b2			/* Transfer clock rate select bit */
#define		mss_sscrh	sscrh_addr.bit.b5			/* Master/Slave device select bit */
#define		rsstp_sscrh	sscrh_addr.bit.b6			/* Receive single stop bit */

/*------------------------------------------------------
  IIC bus control register 1
------------------------------------------------------*/
union	byte_def	iccr1_addr;
#define		iccr1		iccr1_addr.byte

#define		cks0_iccr1	iccr1_addr.bit.b0			/* Transmit clock select bit 3 to 0 */
#define		cks1_iccr1	iccr1_addr.bit.b1			/* Transmit clock select bit 3 to 0 */
#define		cks2_iccr1	iccr1_addr.bit.b2			/* Transmit clock select bit 3 to 0 */
#define		cks3_iccr1	iccr1_addr.bit.b3			/* Transmit clock select bit 3 to 0 */
#define		trs_iccr1	iccr1_addr.bit.b4			/* Transfer/receive select bit */
#define		mst_iccr1	iccr1_addr.bit.b5			/* Master/slave select bit */
#define		rcvd_iccr1	iccr1_addr.bit.b6			/* Receive disable bit */
#define		ice_iccr1	iccr1_addr.bit.b7			/* IIC bus interface enable bit */

/*------------------------------------------------------
  SS control register L
------------------------------------------------------*/
union	byte_def	sscrl_addr;
#define		sscrl		sscrl_addr.byte

#define		sres_sscrl	sscrl_addr.bit.b1			/* Clock synchronous serial I/O with chip select control part reset bit */
#define		solp_sscrl	sscrl_addr.bit.b4			/* SOL write protect bit */
#define		sol_sscrl	sscrl_addr.bit.b5			/* Serial data output value setting bit */

/*------------------------------------------------------
  IIC bus control register 2
------------------------------------------------------*/
union	byte_def	iccr2_addr;
#define		iccr2		iccr2_addr.byte

#define		iicrst_iccr2	iccr2_addr.bit.b1		/* IIC control part reset bit */
#define		sclo_iccr2		iccr2_addr.bit.b3		/* SCL monitor flag */
#define		sdaop_iccr2		iccr2_addr.bit.b4		/* SDAO write protect bit */
#define		sdao_iccr2		iccr2_addr.bit.b5		/* SDA output value control bit */
#define		scp_iccr2		iccr2_addr.bit.b6		/* Start/Stop condition generation disable bit */
#define		bbsy_iccr2		iccr2_addr.bit.b7		/* Bus busy bit */

/*------------------------------------------------------
  SS mode register
------------------------------------------------------*/
union	byte_def	ssmr_addr;
#define		ssmr		ssmr_addr.byte

#define		bc0_ssmr	ssmr_addr.bit.b0			/* Bit counter 2 to 0*/
#define		bc1_ssmr	ssmr_addr.bit.b1			/* Bit counter 2 to 0*/
#define		bc2_ssmr	ssmr_addr.bit.b2			/* Bit counter 2 to 0*/
#define		cphs_ssmr	ssmr_addr.bit.b5			/* SSCK clock phase select bit */
#define		cpos_ssmr	ssmr_addr.bit.b6			/* SSCK clock polarity select bit */
#define		mls_ssmr	ssmr_addr.bit.b7			/* MSB first/ LSB first select bit */

/*------------------------------------------------------
  IIC bus mode register
------------------------------------------------------*/
union	byte_def	icmr_addr;
#define		icmr		icmr_addr.byte

#define		bc0_icmr	icmr_addr.bit.b0			/* Bit counter 2 to 0 */
#define		bc1_icmr	icmr_addr.bit.b1			/* Bit Counter 2 to 0 */
#define		bc2_icmr	icmr_addr.bit.b2			/* Bit Counter 2 to 0 */
#define		bcwp_icmr	icmr_addr.bit.b3			/* BC write protect bit */
#define		wait_icmr	icmr_addr.bit.b6			/* Wait insertion bit */
#define		mls_icmr	icmr_addr.bit.b7			/* MSB-First/LSB-First select */

/*------------------------------------------------------
  SS enable register 
------------------------------------------------------*/
union	byte_def	sser_addr;
#define		sser		sser_addr.byte

#define		ceie_sser	sser_addr.bit.b0			/* Conflict error interrupt enable bit */
#define		re_sser		sser_addr.bit.b3			/* Receive enable bit */
#define		te_sser		sser_addr.bit.b4			/* Transmit enable bit */
#define		rie_sser	sser_addr.bit.b5			/* Receive interrupt enable bit */
#define		teie_sser	sser_addr.bit.b6			/* Transmit end interrupt enable bit */
#define		tie_sser	sser_addr.bit.b7			/* Transmit interrupt enable bit */


/*------------------------------------------------------
  IIC bus interrupt enable register
------------------------------------------------------*/
union	byte_def	icier_addr;
#define		icier		icier_addr.byte

#define		ackbt_icier	icier_addr.bit.b0			/* Transmit acknow ledge select bit */
#define		ackbr_icier	icier_addr.bit.b1			/* Receive acknow ledge bit */
#define		acke_icier	icier_addr.bit.b2			/* Acknowledge bit judgement select bit */
#define		stie_icier	icier_addr.bit.b3			/* Stop condition detection interrupt enable bit */
#define		nakie_icier	icier_addr.bit.b4			/* NACK receive interrupt enable bit */
#define		rie_icier	icier_addr.bit.b5			/* Receive interrupt enable bit */
#define		teie_icier	icier_addr.bit.b6			/* Transmit end interrupt enable bit */
#define		tie_icier	icier_addr.bit.b7			/* Transmit interrupt enable bit */

/*------------------------------------------------------
  SS status register
------------------------------------------------------*/
union	byte_def	sssr_addr;
#define		sssr		sssr_addr.byte

#define		ce_sssr		sssr_addr.bit.b0			/* Conflict error flag */
#define		orer_sssr	sssr_addr.bit.b2			/* Overrun error flag */
#define		rdrf_sssr	sssr_addr.bit.b5			/* Receive data register full */
#define		tend_sssr	sssr_addr.bit.b6			/* Transmit end */
#define		tdre_sssr	sssr_addr.bit.b7			/* Transmit data empty */

/*------------------------------------------------------
  IIC bus status register
------------------------------------------------------*/
union	byte_def	icsr_addr;
#define		icsr		icsr_addr.byte

#define		adz_icsr	icsr_addr.bit.b0			/* General call address recognition flag */
#define		aas_icsr	icsr_addr.bit.b1			/* Slave address recognition flag */
#define		al_icsr		icsr_addr.bit.b2			/* Arbitration lost flag / Overrun error flag */
#define		stop_icsr	icsr_addr.bit.b3			/* Stop condition detection flag */
#define		nackf_icsr	icsr_addr.bit.b4			/* No acknow ledge detection flag */
#define		rdrf_icsr	icsr_addr.bit.b5			/* Receive data register full */
#define		tend_icsr	icsr_addr.bit.b6			/* Transmit end */
#define		tdre_icsr	icsr_addr.bit.b7			/* Transmit data empty */

/*------------------------------------------------------
  SS mode register 2
------------------------------------------------------*/
union	byte_def	ssmr2_addr;
#define		ssmr2		ssmr2_addr.byte

#define		ssums_ssmr2	ssmr2_addr.bit.b0			/* Clock synchronous serial I/O with chip select mode select bit */
#define		csos_ssmr2	ssmr2_addr.bit.b1			/* SCS pin open drain output select bit */
#define		soos_ssmr2	ssmr2_addr.bit.b2			/* SSO pin open drain output select bit */
#define		sckos_ssmr2	ssmr2_addr.bit.b3			/* SSCK pin open drain output select bit */
#define		css0_ssmr2	ssmr2_addr.bit.b4			/* SCS pin selsct bit */
#define		css1_ssmr2	ssmr2_addr.bit.b5			/* SCS pin select bit */
#define		scks_ssmr2	ssmr2_addr.bit.b6			/* SSCK pin select bit */
#define		bide_ssmr2	ssmr2_addr.bit.b7			/* Bidirectional mode enable bit */

/*------------------------------------------------------
  Slave address register
------------------------------------------------------*/
union	byte_def	sar_addr;
#define		sar			sar_addr.byte

#define		fs_sar		sar_addr.bit.b0				/* Format select bit */
#define		sva0_sar	sar_addr.bit.b1				/* Slave address 6 to 0 */
#define		sva1_sar	sar_addr.bit.b2				/* Slave address 6 to 0 */
#define		sva2_sar	sar_addr.bit.b3				/* Slave address 6 to 0 */
#define		sva3_sar	sar_addr.bit.b4				/* Slave address 6 to 0 */
#define		sva4_sar	sar_addr.bit.b5				/* Slave address 6 to 0 */
#define		sva5_sar	sar_addr.bit.b6				/* Slave address 6 to 0 */
#define		sva6_sar	sar_addr.bit.b7				/* Slave address 6 to 0 */

/*------------------------------------------------------
  SS transmit data register
------------------------------------------------------*/
union	byte_def	sstdr_addr;
#define		sstdr		sstdr_addr.byte

/*------------------------------------------------------
  IIC bus transmit data register
------------------------------------------------------*/
union	byte_def	icdrt_addr;
#define		icdrt		icdrt_addr.byte

/*------------------------------------------------------
  SS receive data register
------------------------------------------------------*/
union	byte_def	ssrdr_addr;
#define		ssrdr		ssrdr_addr.byte

/*------------------------------------------------------
  IIC bus receive data register
------------------------------------------------------*/
union	byte_def	icdrr_addr;
#define		icdrr		icdrr_addr.byte

/*------------------------------------------------------
  D-A register 0
------------------------------------------------------*/
union	byte_def	da0_addr;
#define		da0			da0_addr.byte

/*------------------------------------------------------
  D-A register 1
------------------------------------------------------*/
union	byte_def	da1_addr;
#define		da1			da1_addr.byte

/*------------------------------------------------------
  D-A control register
------------------------------------------------------*/
union	byte_def	dacon_addr;
#define		dacon		dacon_addr.byte

#define		da0e_dacon	dacon_addr.bit.b0			/* D/A 0 output enable bit */
#define		da1e_dacon	dacon_addr.bit.b1			/* D/A 1 output enable bit */

/*------------------------------------------------------
  Port P0 register
------------------------------------------------------*/
union	byte_def	p0_addr;
#define		p0			p0_addr.byte

#define		p0_0		p0_addr.bit.b0				/* Port P00 bit */
#define		p0_1		p0_addr.bit.b1				/* Port P01 bit */
#define		p0_2		p0_addr.bit.b2				/* Port P02 bit */
#define		p0_3		p0_addr.bit.b3				/* Port P03 bit */
#define		p0_4		p0_addr.bit.b4				/* Port P04 bit */
#define		p0_5		p0_addr.bit.b5				/* Port P05 bit */
#define		p0_6		p0_addr.bit.b6				/* Port P06 bit */
#define		p0_7		p0_addr.bit.b7				/* Port P07 bit */

/*------------------------------------------------------
  Port P0 direction register
------------------------------------------------------*/
union	byte_def	pd0_addr;
#define		pd0			pd0_addr.byte

#define		pd0_0		pd0_addr.bit.b0				/* Port P00 direction bit */
#define		pd0_1		pd0_addr.bit.b1				/* Port P01 direction bit */
#define		pd0_2		pd0_addr.bit.b2				/* Port P02 direction bit */
#define		pd0_3		pd0_addr.bit.b3				/* Port P03 direction bit */
#define		pd0_4		pd0_addr.bit.b4				/* Port P04 direction bit */
#define		pd0_5		pd0_addr.bit.b5				/* Port P05 direction bit */