r8c2a.h

这是一个用Ｔ108加上瑞萨公司Ｒ8Ｃ2Ａ做的一个ＯＳＤ显示。希望能帮上大家。

#pragma	ADDRESS		trcgrd_addr		012EH	/* Timer RC general register D */

#pragma	ADDRESS		trccr2_addr		0130H	/* Timer RC control register 2 */

#pragma	ADDRESS		trcdf_addr		0131H	/* Timer RC digital filter function selection register */

#pragma	ADDRESS		trcoer_addr		0132H	/* Timer RC output master enable register */

#pragma	ADDRESS		trdstr_addr		0137H	/* Timer RD start register */

#pragma	ADDRESS		trdmr_addr		0138H	/* Timer RD mode register */

#pragma	ADDRESS		trdpmr_addr		0139H	/* Timer RD PWM mode register */

#pragma	ADDRESS		trdfcr_addr		013AH	/* Timer RD function control register */

#pragma	ADDRESS		trdoer1_addr	013BH	/* Timer RD output master enable register 1 */

#pragma	ADDRESS		trdoer2_addr	013CH	/* Timer RD output master enable register 2 */

#pragma	ADDRESS		trdocr_addr		013DH	/* Timer RD output control register */

#pragma	ADDRESS		trddf0_addr		013EH	/* Timer RD digital filter function selection register 0 */

#pragma	ADDRESS		trddf1_addr		013FH	/* Timer RD digital filter function selection register 1 */

#pragma	ADDRESS		trdcr0_addr		0140H	/* Timer RD control register 0 */

#pragma	ADDRESS		trdiora0_addr	0141H	/* Timer RD I/O contorol register A0 */

#pragma	ADDRESS		trdiorc0_addr	0142H	/* Timer RD I/O contorol register C0 */

#pragma	ADDRESS		trdsr0_addr		0143H	/* Timer RD status register 0 */

#pragma	ADDRESS		trdier0_addr	0144H	/* Timer RD interrupt enable register 0 */

#pragma	ADDRESS		trdpocr0_addr	0145H	/* Timer RD PWM mode output level control register 0 */

#pragma	ADDRESS		trd0_addr		0146H	/* Timer RD counter 0 */

#pragma	ADDRESS		trdgra0_addr	0148H	/* Timer RD general register A0 */

#pragma	ADDRESS		trdgrb0_addr	014AH	/* Timer RD general register B0 */

#pragma	ADDRESS		trdgrc0_addr	014CH	/* Timer RD general register C0 */

#pragma	ADDRESS		trdgrd0_addr	014EH	/* Timer RD general register D0 */

#pragma	ADDRESS		trdcr1_addr		0150H	/* Timer RD control register 1 */

#pragma	ADDRESS		trdiora1_addr	0151H	/* Timer RD I/O contorol register A1 */

#pragma	ADDRESS		trdiorc1_addr	0152H	/* Timer RD I/O contorol register C1 */

#pragma	ADDRESS		trdsr1_addr		0153H	/* Timer RD status register 1 */

#pragma	ADDRESS		trdier1_addr	0154H	/* Timer RD interrupt enable register 1 */

#pragma	ADDRESS		trdpocr1_addr	0155H	/* Timer RD PWM mode output level control register 1 */

#pragma	ADDRESS		trd1_addr		0156H	/* Timer RD counter 1 */

#pragma	ADDRESS		trdgra1_addr	0158H	/* Timer RD general register A1 */

#pragma	ADDRESS		trdgrb1_addr	015AH	/* Timer RD general register B1 */

#pragma	ADDRESS		trdgrc1_addr	015CH	/* Timer RD general register C1 */

#pragma	ADDRESS		trdgrd1_addr	015EH	/* Timer RD general register D1 */

#pragma	ADDRESS		u2mr_addr		0160H	/* UART0 transmit/receive mode register */

#pragma	ADDRESS		u2brg_addr		0161H	/* UART0 bit rate register */

#pragma	ADDRESS		u2tb_addr		0162H	/* UART0 transmit buffer register */

#pragma	ADDRESS		u2c0_addr		0164H	/* UART0 transmit/receive control register 0 */

#pragma	ADDRESS		u2c1_addr		0165H	/* UART0 transmit/receive control register 1 */

#pragma	ADDRESS		u2rb_addr		0166H	/* UART0 receive buffer register */

#pragma	ADDRESS		fmr4_addr		01B3H	/* Flash memory control register 4 */

#pragma	ADDRESS		fmr1_addr		01B5H	/* Flash memory control register 1 */

#pragma	ADDRESS		fmr0_addr		01B7H	/* Flash memory control register 0 */

#pragma	ADDRESS		trf_addr		0290H	/* Timer RF register */

#pragma	ADDRESS		trfcr0_addr		029AH	/* Timer RF control register 0 */

#pragma	ADDRESS		trfcr1_addr		029BH	/* Timer RF control register 1 */

#pragma	ADDRESS		trfm0_addr		029CH	/* capture/compare0 register */

#pragma	ADDRESS		trfm1_addr		029EH	/* capture/compare1 register */

#pragma	ADDRESS		ad0_addr		02C0H	/* A-D register 0 */

#pragma	ADDRESS		adcon2_addr		02D4H	/* A-D control register 2 */

#pragma	ADDRESS		adcon0_addr		02D6H	/* A-D control register 0 */

#pragma	ADDRESS		adcon1_addr		02D7H	/* A-D control register 1 */

#pragma	ADDRESS		pd8_addr		02E4H	/* Port P8 direction register */

#pragma	ADDRESS		p8_addr			02E6H	/* Port P8 register */

#pragma	ADDRESS		pur2_addr		02FCH	/* Pull-up control register2 */

#pragma	ADDRESS		trfout_addr		02FFH	/* Timer RF output control register */




/********************************************************
*  declare SFR bit                                      *
********************************************************/
struct	bit_def {
	char	b0:1;
	char	b1:1;
	char	b2:1;
	char	b3:1;
	char	b4:1;
	char	b5:1;
	char	b6:1;
	char	b7:1;
};
union	byte_def{
	struct	bit_def bit;
	char	byte;
};

/*------------------------------------------------------
  Processor mode register0
------------------------------------------------------*/
union	byte_def	pm0_addr;
#define		pm0			pm0_addr.byte

#define		pm03		pm0_addr.bit.b3				/* Software reset bit */

/*------------------------------------------------------
  Processor mode register1
------------------------------------------------------*/
union	byte_def	pm1_addr;
#define		pm1			pm1_addr.byte

#define		pm12		pm1_addr.bit.b2				/* WDT interrupt/reset switch bit */

/*------------------------------------------------------
  System clock control register0
------------------------------------------------------*/
union	byte_def	cm0_addr;
#define		cm0			cm0_addr.byte

#define		cm02		cm0_addr.bit.b2				/* WAIT peripheral function clock stop bit */
#define		cm03		cm0_addr.bit.b3				/* XCIN-XCOUT drive capacity select bit */
#define		cm04		cm0_addr.bit.b4				/* Port XC Switch bit */
#define		cm05		cm0_addr.bit.b5				/* Xin clock (Xin-Xout) stop bit */
#define		cm06		cm0_addr.bit.b6				/* System clock division select bit0 */
#define		cm07		cm0_addr.bit.b7				/* CPU Clock Select bit */

/*------------------------------------------------------
  System clock control register1
------------------------------------------------------*/
union	byte_def	cm1_addr;
#define		cm1			cm1_addr.byte

#define		cm10		cm1_addr.bit.b0				/* All clock stop control bit */
#define		cm11		cm1_addr.bit.b1				/* XIN-XOUT internal resistor select bit */
#define		cm12		cm1_addr.bit.b2				/* XCIN-XCOUT internal resistor select bit */
#define		cm13		cm1_addr.bit.b3				/* Port Xin-Xout switch bit */
#define		cm14		cm1_addr.bit.b4				/* Low-speed on-chip oscillation stop bit */
#define		cm15		cm1_addr.bit.b5				/* Xin-Xout drive capacity select bit */
#define		cm16		cm1_addr.bit.b6				/* System clock division select bit1 */
#define		cm17		cm1_addr.bit.b7				/* System clock division select bit1 */

/*------------------------------------------------------
  Module standby control register
------------------------------------------------------*/
union	byte_def	mstcr_addr;
#define		mstcr		mstcr_addr.byte

#define		mstiic		mstcr_addr.bit.b3			/* I2C Bus stanby bit */
#define		msttrd		mstcr_addr.bit.b4			/* Timer RD stanby bit */
#define		msttrc		mstcr_addr.bit.b5			/* Timer RC stanby bit */

/*------------------------------------------------------
  Protect register
------------------------------------------------------*/
union	byte_def	prcr_addr;
#define		prcr		prcr_addr.byte

#define		prc0		prcr_addr.bit.b0			/* Protect bit0 */
#define		prc1		prcr_addr.bit.b1			/* Protect bit1 */
#define		prc2		prcr_addr.bit.b2			/* Protect bit2 */
#define		prc3		prcr_addr.bit.b3			/* Protect bit3 */

/*------------------------------------------------------
  Oscillation stop detection register
------------------------------------------------------*/
union	byte_def	ocd_addr;
#define		ocd			ocd_addr.byte

#define		ocd0		ocd_addr.bit.b0				/* Oscillation stop detection enable bit */
#define		ocd1		ocd_addr.bit.b1				/* Oscillation stop detection interrupt enable bit */
#define		ocd2		ocd_addr.bit.b2				/* System clock select bit */
#define		ocd3		ocd_addr.bit.b3				/* Clock monitor bit */

/*------------------------------------------------------
  Watchdog timer reset register
------------------------------------------------------*/
union	byte_def	wdtr_addr;
#define		wdtr		wdtr_addr.byte

/*------------------------------------------------------
  Watchdog timer start register
------------------------------------------------------*/
union	byte_def	wdts_addr;
#define		wdts		wdts_addr.byte

/*------------------------------------------------------
  Watchdog timer control register
------------------------------------------------------*/
union	byte_def	wdc_addr;
#define		wdc			wdc_addr.byte

#define		wdc7		wdc_addr.bit.b7				/* Prescaler select bit */

/*------------------------------------------------------
  Address match interrupt enable register
------------------------------------------------------*/
union	byte_def	aier_addr;
#define		aier		aier_addr.byte

#define		aier0		aier_addr.bit.b0			/* Address match interrupt 0 enable bit */
#define		aier1		aier_addr.bit.b1			/* Address match interrupt 1 enable bit */


/*------------------------------------------------------
  Count source protection mode register
------------------------------------------------------*/
union	byte_def	cspr_addr;
#define		cspr		cspr_addr.byte
#define		cspro		cspr_addr.bit.b7			/* Count source protection mode select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 0
------------------------------------------------------*/
union	byte_def	fra0_addr;
#define		fra0		fra0_addr.byte

#define		fra00		fra0_addr.bit.b0			/* High-speed on-chip oscillator enable bit */
#define		fra01		fra0_addr.bit.b1			/* High-speed on-chip oscillator select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 1
------------------------------------------------------*/
union	byte_def	fra1_addr;
#define		fra1		fra1_addr.byte

/*------------------------------------------------------
  High-speed on-chip oscillator control register 2
------------------------------------------------------*/
union	byte_def	fra2_addr;
#define		fra2		fra2_addr.byte

#define		fra20		fra2_addr.bit.b0			/* High-speed on-chip oscillator frequency switching bit */
#define		fra21		fra2_addr.bit.b1			/* High-speed on-chip oscillator frequency switching bit */
#define		fra22		fra2_addr.bit.b2			/* High-speed on-chip oscillator frequency switching bit */

/*------------------------------------------------------
  Clock prescaler reset flag
------------------------------------------------------*/
union	byte_def	cpsrf_addr;
#define		cpsrf		cpsrf_addr.byte

#define		cpsr		cpsrf_addr.bit.b7			/* Clock prescaler reset flag */

/*------------------------------------------------------
  Voltage detection register 1
------------------------------------------------------*/
union	byte_def	vca1_addr;
#define		vca1		vca1_addr.byte

#define		vca13		vca1_addr.bit.b3			/* Voltage detection 2 signal monitor flag */

/*------------------------------------------------------
  Voltage detection register 2
------------------------------------------------------*/
union	byte_def	vca2_addr;
#define		vca2		vca2_addr.byte

#define		vca20		vca2_addr.bit.b0			/* Internal power low consumption enable bit */
#define		vca25		vca2_addr.bit.b5			/* Voltage detection 0 enable bit */
#define		vca26		vca2_addr.bit.b6			/* Voltage detection 1 enable bit */