mxc_setup_mx31.h

i.mx31 3DS平台Nandboot引导程序源码

 #define         EUartUSR2_IRINT     (1 << 8)    // Serial infrared interrupt flag
 #define         EUartUSR2_WAKE      (1 << 7)    // Wake
 #define         EUartUSR2_RTSF      (1 << 4)    // RTS edge interrupt flag
 #define         EUartUSR2_TXDC      (1 << 3)    // Transmitter complete
 #define         EUartUSR2_BRCD      (1 << 2)    // Break condition
 #define         EUartUSR2_ORE       (1 << 1)    // Overrun error
 #define         EUartUSR2_RDR       (1 << 0)    // Recv data ready
 #define         EUartUTS_FRCPERR    (1 << 13)   // Force parity error
 #define         EUartUTS_LOOP       (1 << 12)   // Loop tx and rx
 #define         EUartUTS_TXEMPTY    (1 << 6)    // TxFIFO empty
 #define         EUartUTS_RXEMPTY    (1 << 5)    // RxFIFO empty
 #define         EUartUTS_TXFULL     (1 << 4)    // TxFIFO full
 #define         EUartUTS_RXFULL     (1 << 3)    // RxFIFO full
 #define         EUartUTS_SOFTRST    (1 << 0)    // Software reset
 
 #define         DelayTimerPresVal   3
 
 #define         L2CC_ENABLED
 
 /* Assuming 26MHz input clock */
 /*                         PD          MFD           MFI          MFN */
 #define         MPCTL_PARAM_208  ((1 << 26) + (0   << 16) + (8  << 10) + (0 << 0))
 #define         MPCTL_PARAM_399  ((0 << 26) + (51  << 16) + (7  << 10) + (35 << 0))
 #define	MPCTL_PARAM_532  	((0 << 26) + (51  << 16) + (10 << 10) + (12 << 0))
 #define	CCM_CCMR		0x074B0B7C
 /* UPCTL USB PLL */
 #define	UPCTL_PARAM_240  	(((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
 
 /* UPCTL                   PD             MFD              MFI          MFN */
 #define UPCTL_PARAM_288  (((1-1) << 26) + ((13-1) << 16) + (5  << 10) + (7  << 0))
 
 /* PDR0 */
 #define PDR0_208_104_52     0xFF870D48  /* ARM=208MHz, HCLK=104MHz, IPG=52MHz
 */
 #define PDR0_399_66_66      0xFF872B28  /* ARM=399MHz, HCLK=IPG=66.5MHz */
 #define PDR0_399_133_66     0xFF871650  /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */
 #define PDR0_532_133_66     0xFF871D58  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz*/
 #define PDR0_665_83_66      0xFF873D78  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz
 */
 #define PDR0_665_133_66     0xFF872660  /* ARM=532MHz, HCLK=133MHz, IPG=66MHz
 */
 
 #define PBC_BASE            CS4_BASE_ADDR    /* Peripheral Bus Controller */
 
 #define PBC_BSTAT2                   0x2
 #define PBC_BCTRL1                   0x4
 #define PBC_BCTRL1_CLR               0x6
 #define PBC_BCTRL2                   0x8
 #define PBC_BCTRL2_CLR               0xA
 #define PBC_BCTRL3                   0xC
 #define PBC_BCTRL3_CLR               0xE
 #define PBC_BCTRL4                   0x10
 #define PBC_BCTRL4_CLR               0x12
 #define PBC_BSTAT1                   0x14
 #define         MX31EVB_CS_LAN_BASE        (CS4_BASE_ADDR + 0x00020000 +  0x300)
 #define         MX31EVB_CS_UART_BASE       (CS4_BASE_ADDR + 0x00010000)
 
 #define         REDBOOT_IMAGE_SIZE              0x40000
 
 #define         SDRAM_WORKAROUND_FULL_PAGE
 
 #define       ARMHIPG_208_52_52         /* ARM: 208MHz, HCLK=IPG=52MHz*/
 #define       ARMHIPG_52_52_52          /* ARM: 52MHz, HCLK=IPG=52MHz*/
 #define       ARMHIPG_399_66_66
 #define         ARMHIPG_399_133_66
 
 /* MX31 EVB SDRAM is from 0x80000000, 64M */
 #define         SDRAM_BASE_ADDR                 CSD0_BASE_ADDR
 #define         SDRAM_SIZE                      0x04000000
 
 #define         UART_WIDTH_32         /* internal UART is 32bit access only */
 #define         EXT_UART_x16
 
 #define         UART_WIDTH_32         /* internal UART is 32bit access only */
 
 #define         FLASH_BURST_MODE_ENABLE 1
 #define         SDRAM_COMPARE_CONST1    0x55555555
 #define         SDRAM_COMPARE_CONST2    0xAAAAAAAA
 #define         UART_FIFO_CTRL          0x881
 #define         TIMEOUT                 1000
 
 /* moved from uart.c file */
 
#if !defined(__ASSEMBLER__) //ADDED FOR COMPILATION
#define SETUP_IOMUX()         setup_iomux()
 // Jason: Copy from Redboot source code
 static void setup_iomux(void)
 {
                       int i;
                       int dummy;
         
                       writew(0x8023, PBC_BASE + PBC_BCTRL1);
                       for (i=0; i < 100000; i++)
                       {
                       }
                       writew(0x00DF, PBC_BASE + PBC_BCTRL1_CLR);
                       for (i=0; i < 100000; i++)
                       {
                       }
                       dummy = readb(0xB4000008);
                       dummy = readb(0xB4000007);
                       dummy = readb(0xB4000008);
                       dummy = readb(0xB4000007);
                         
                       // Uart 1 set to OUTPUT/INPUTCONFIG_FUNC
                       writel(0x12121212, IOMUXC_BASE_ADDR + 0x7C);
                       //writel(0x12121212, IOMUXC_BASE_ADDR + 0x78);
                       writel(0x12121212, IOMUXC_BASE_ADDR + 0x80);
                       writel(0x12121212, IOMUXC_BASE_ADDR + 0x7C);

}
#endif
                         
#if defined(__ASSEMBLER__) //ADDED FOR COMPILATION
/* 
 * Platform setup macro
 */
#define PLATFORM_SETUP1 _platform_setup1

/* This macro represents the initial startup code for the platform */
        .macro  _platform_setup1
MX31_SETUP_START:
         /*
          * - set correct memory timings & bus widths
          * - configure chip select lines
          * - init anything that could be undefined after reset
          */
 /*
  * Step 1: ARM1136 init
  *       - invalidate I/D cache/TLB and drain write buffer;
  *       - invalidate L2 cache
  *       - unaligned access
  *       - branch predictions
 */
 #ifdef TURN_OFF_IMPRECISE_ABORT
         mrs r0, cpsr
         bic r0, r0, #0x100
         msr cpsr, r0
 #endif
 
         mov r0, #0
         mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
         mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
         mcr 15, 0, r0, c7, c10, 4        /* Drain the write buffer */
 
         /* Also setup the Peripheral Port Remap register inside the core */
         ldr r0, =0x40000015        /* start from AIPS 2GB region */
         mcr p15, 0, r0, c15, c2, 4
 
         /*** L2 Cache setup/invalidation/disable ***/
          /* Disable L2 cache first */
         ldr r0, =L2CC_BASE_ADDR
         ldr r2, [r0, #L2_CACHE_CTL_REG]
         bic r2, r2, #0x1
         str r2, [r0, #L2_CACHE_CTL_REG]
 
         /*
          * Configure L2 Cache:
          * - 128k size(16k way)
          * - 8-way associativity
          * - 0 ws TAG/VALID/DIRTY
          * - 4 ws DATA R/W
           */
         ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
        and r1, r1, #0xFE000000
        ldr r2, =0x00030024
        orr r1, r1, r2
        str r1, [r0, #L2_CACHE_AUX_CTL_REG]

        /* Invalidate L2 */
         ldr r1, =0x000000FF
        str r1, [r0, #L2_CACHE_INV_WAY_REG]
 L2_loop:
         /* Poll Invalidate By Way register */
         ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
         cmp r2, #0
         bne L2_loop
         /*** End of L2 operations ***/
 
 /*
  * End of Step 1: ARM1136 init
  */
 
 /*
  * Step 2: AIPI setup
  *        Only setup MPROTx registers. The PACR default values are good.
  */
         /*
          * Set all MPROTx to be non-bufferable, trusted for R/W,
          * not forced to user-mode.
          */
         ldr r0, =AIPS1_CTRL_BASE_ADDR
         ldr r1, =0x77777777
         str r1, [r0, #0x00]
         str r1, [r0, #0x04]
         ldr r0, =AIPS2_CTRL_BASE_ADDR
         str r1, [r0, #0x00]
         str r1, [r0, #0x04]
 
         /*
          * Clear the on and off peripheral modules Supervisor Protect bit
          * for SDMA to access them. Did not change the AIPS control registers
          * (offset 0x20) access type
          */
         ldr r0, =AIPS1_CTRL_BASE_ADDR
         ldr r1, =0x0
         str r1, [r0, #0x40]
         str r1, [r0, #0x44]
         str r1, [r0, #0x48]
        str r1, [r0, #0x4C]
         ldr r1, [r0, #0x50]
         and r1, r1, #0x00FFFFFF
         str r1, [r0, #0x50]
 
         ldr r0, =AIPS2_CTRL_BASE_ADDR
         ldr r1, =0x0
         str r1, [r0, #0x40]
         str r1, [r0, #0x44]
         str r1, [r0, #0x48]
         str r1, [r0, #0x4C]
         ldr r1, [r0, #0x50]
         and r1, r1, #0x00FFFFFF
         str r1, [r0, #0x50]
 /*
  * End of Step 2: AIPI setup
  */
 
 /*
  * Step 3: MAX (Multi-Layer AHB Crossbar Switch) setup
  */
         ldr r0, =MAX_BASE_ADDR
         /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
         ldr r1, =0x00302154
         str r1, [r0, #0x000]        /* for S0 */
         str r1, [r0, #0x100]        /* for S1 */
         str r1, [r0, #0x200]        /* for S2 */
         str r1, [r0, #0x300]        /* for S3 */
         str r1, [r0, #0x400]        /* for S4 */
         /* SGPCR - always park on last master */
         ldr r1, =0x10
         str r1, [r0, #0x010]        /* for S0 */
         str r1, [r0, #0x110]        /* for S1 */
         str r1, [r0, #0x210]        /* for S2 */
         str r1, [r0, #0x310]        /* for S3 */
         str r1, [r0, #0x410]        /* for S4 */
         /* MGPCR - restore default values */
         ldr r1, =0x0
         str r1, [r0, #0x800]        /* for M0 */
         str r1, [r0, #0x900]        /* for M1 */
         str r1, [r0, #0xA00]        /* for M2 */
         str r1, [r0, #0xB00]        /* for M3 */
         str r1, [r0, #0xC00]        /* for M4 */
         str r1, [r0, #0xD00]        /* for M5 */
 /*
  * End of Step 3: MAX setup
  */
 
 /*
  * Step 4: setup SPBA to allow all 3 masters to have access to these shared
  peripherals
  */
         ldr r0, =SPBA_CTRL_BASE_ADDR
         ldr r1, =0x7            /* allow all 3 masters access */
         /* Do nothing. The default setting is good */
 /*
  * End of Step 4: SPBA setup
  */
 
 /*
  * Step 5: Clock setup
  */
 
        ldr r0, =IPU_CTRL_BASE_ADDR
        ldr r1, =0x40
         str r1, [r0]
 
        /* RVAL/WVAL for L2 cache memory */
         ldr r0, =0x515
         ldr r1, =CLKCTL_BASE_ADDR
         str r0, [r1, #0x10]
 
         ldr r0, =CRM_MCU_BASE_ADDR
         ldr r1, =CCM_CCMR //0x074B0B7B /* select CLKL to be source */
         str r1, [r0, #CLKCTL_CCMR]   /* Select 26MHz clock as ref clk. SPLL
         for FIR */
 
 #if 0
         /* If SDRAM has been setup, bypass clock/WEIM setup */
         cmp pc, #SDRAM_BASE_ADDR
         blt init_sdram
         cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
         blt HWInitialise_skip_SDRAM_setup
 #endif
 
         // 532-133-66.5
         ldr r1, =PDR0_532_133_66
         str r1, [r0, #CLKCTL_PDR0]
         ldr r1, =MPCTL_PARAM_532
         str r1, [r0, #CLKCTL_MPCTL]
 
         /* Set UPLL=240MHz, USB=60MHz */
         ldr r1, =0x49FCFE7F
         str r1, [r0, #CLKCTL_PDR1]
         ldr r1, =UPCTL_PARAM_240
         str r1, [r0, #CLKCTL_UPCTL]
 /*
  * End of Step 5: Clock setup
  */
 
#ifdef BOOT_TIME
	ldr r0, =EPIT1_BASE_ADDR
	ldr r1, =0x030201F1
	str r1, [r0, #0]
	ldr r1, =0xFFFFFFFF
	str r1, [r0, #0x08]
#endif