mxc_setup_mx21.h

i.mx31 3DS平台Nandboot引导程序源码

#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     4
#define         IP_DIV      8
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          APCLK_399_133_66
#define         ADPLL_PDF   (1)
#define         ADPLL_MFI   (6)
#define         ADPLL_MFN   (-105)
#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     3
#define         IP_DIV      6
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          APCLK_266_133_66
#define         ADPLL_PDF   (2)
#define         ADPLL_MFI   (8)
#define         ADPLL_MFN   (-140)
#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     2
#define         IP_DIV      4
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          USB_PLL_CLK_96
#define         UDPLL_PDF   (1)
#define         UDPLL_MFI   (5)
#define         UDPLL_MFN   (7142)
#define         UDPLL_MFD   (10000 - 1)
#define         UDPLL_OP    ((UDPLL_MFI << 4) | (UDPLL_PDF - 1))
#define         USB_DIV     0       /* 0 => /2 */
#define         FIRI_DIV    1       /* 1 => /2 */
#define         CS_DIV      0x19    /* 0x19 => /12.5 */
#endif
#define         TIMEOUT                 4000

/* MX21 EVB SDRAM is from 0x80000000, 64M */
#define         SDRAM_BASE_ADDR         0xc0000000

#ifdef  SDRAM_X32
#define          SDRAM_SIZE              0x04000000
#else
#define          SDRAM_SIZE              0x02000000
#endif //SDRAM_X32

#if !defined(__ASSEMBLER__) //ADDED FOR COMPILATION

//#define MX2ADS_IO_IOBASE 	//0xe4000000
#define MX2ADS_EMI_IOBASE           	0xDF000000
//#define IO_ADDRESS(x) 			x   //(((x)-0x10000000)+MX2ADS_IO_IOBASE)		//This Macro only for map register space to 0xe4000000;
//#define MX2_IO_ADDRESS    IO_ADDRESS


//#########################################		
//# GPIO                                  #		
//# $1001_5000 to $1001_5FFF              #		
//#########################################

#define GPIOA	0
#define GPIOB	1
#define GPIOC	2
#define GPIOD	3
#define GPIOE	4
#define GPIOF	5

/* Use as GPIO_BASE_ADDR(GPIOA)- GPIO_BASE_ADDR(GPIOF)*/
#define GPIO_BASE_ADDR(x)	(0x10015000+x*0x100)
#define _reg_GPIO_GIUS(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x20)))  //  32bit gpio pta in use reg
#define _reg_GPIO_GPR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x38)))  //  32bit gpio pta general purpose reg


#define CRM_BASE_ADDR	0x10027000	
#define _reg_CRM_CSCR	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x00)))  //  32bit Clock Source Control Reg
#define _reg_CRM_MPCTL0	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x04)))  //  32bit MCU PLL Control Reg
#define _reg_CRM_PCDR0	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x18)))  //  32bit Serial Perpheral Clk Div Reg
#define _reg_CRM_PCDR1	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x1C))) 
#define _reg_CRM_PCCR0	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x20)))  

#define SYS_BASE_ADDR	0x10027800
#define _reg_SYS_FMCR	(*((volatile unsigned long *)(SYS_BASE_ADDR+0x14)))  //  Functional Muxing Control Reg
#define _reg_SYS_PCSR	(*((volatile unsigned long *)(SYS_BASE_ADDR+0x50)))  //  Priority Control/select Reg
#define _reg_SYS_GPCR	(*((volatile unsigned long *)(SYS_BASE_ADDR+0x18)))  //  Global Peripheral Control Reg


#define _reg_WEIM_CSU(x)	(*((volatile unsigned long *)(MX2ADS_EMI_IOBASE+0x1000+8*x)))  //  32bit eim chip sel 0 upper ctr reg
#define _reg_WEIM_CSL(x)	(*((volatile unsigned long *)(MX2ADS_EMI_IOBASE+0x1000+0x04+8*x)))  //  32bit eim chip sel 0 lower ctr reg

#define AIPI1_BASE_ADDR	0x10000000	
#define _reg_AIPI1_PSR0		(*((volatile unsigned long *)(AIPI1_BASE_ADDR+0x00)))	//  32bit Peripheral Size Reg 0
#define _reg_AIPI1_PSR1		(*((volatile unsigned long *)(AIPI1_BASE_ADDR+0x04)))	//  32bit Peripheral Size Reg 1

//#########################################		
//# AIPI2                                 #		
//# $1002_0000 to $1002_0FFF              #		
//#########################################		
#define AIPI2_BASE_ADDR	0x10020000	
#define _reg_AIPI2_PSR0		(*((volatile unsigned long *)(AIPI2_BASE_ADDR+0x00)))  //  32bit Peripheral Size Reg 0
#define _reg_AIPI2_PSR1		(*((volatile unsigned long *)(AIPI2_BASE_ADDR+0x04)))  //  32bit Peripheral Size Reg 1

#define MAX_BASE_ADDR	0x1003F000

#define _reg_MAX_SLV_MPR(x)			(*((volatile unsigned long *)(MAX_BASE_ADDR+0x100*x+0x00)))  //  32bit max slv master priority reg
#define _reg_MAX_SLV_SGPCR(x)		(*((volatile unsigned long *)(MAX_BASE_ADDR+0x100*x+0x10)))  //  32bit max slv0 general ctrl reg



#define SETUP_IOMUX()  setup_iomux()

 static void setup_iomux(void)
 {

 		int temp,tmp;

		if (_reg_SYS_FMCR & 0xC0000000)
	     {
		temp = _reg_CRM_CSCR; 	
		temp |= 0x60000000;		
		_reg_CRM_CSCR = temp; //set PRESC = b11 (i.e. /4) will change to /2 later//  changed for TO2 } 	
		temp = _reg_CRM_CSCR;		
		temp |= 0x00000200;		
		_reg_CRM_CSCR = temp;	//set IPDIV = 1, HCLK divided by 2		
		temp = _reg_CRM_CSCR;		
		temp &= ~0x00003C00;		
		temp |= 0x00000400;	// set BCLKDIV = 1 (i.e. /2)	
		
		_reg_CRM_CSCR = temp;		//PLL input 32.768kHz		
	
		_reg_CRM_MPCTL0 = 0x007b1C73;	// 266M		
		_reg_CRM_CSCR |=0x00200000;
		//wait for the MPLLRESTART bit self clear	
		while (_reg_CRM_CSCR & 0x00200000);
		    _reg_CRM_CSCR &= ~0xe0000000; //set back PRESC = b000 (i.e./1)
		}	
		else
		{

			temp = _reg_CRM_CSCR;
			temp &= ~0xe0000000;	
			temp |= 0x60000000;
			_reg_CRM_CSCR = temp;        //set PRESC = b11 (i.e. /4) will change to /1 later	
			temp = _reg_CRM_CSCR;	
			temp |= 0x00000200;		
			_reg_CRM_CSCR = temp;     	//set IPDIV = 1		
			temp = _reg_CRM_CSCR;		
			temp &= ~0x00003C00;		
			temp |= 0x00000400;	
			_reg_CRM_CSCR = temp;        // set BCLKDIV = 1 (i.e. /2)
			_reg_CRM_CSCR &= ~0xe0000000; //set back PRESC = b000 (i.e./1)
		}

		_reg_CRM_PCDR1 |= 0x5;	
		_reg_CRM_PCDR1 &= 0xFFFFFFC5;

		//enable clock for HCLK BROM and UART_1    
		_reg_CRM_PCCR0 |= 0x10000001;
		
    
	//=================================================================
	// Set up GPIO/IOMUX for UART_1  
	_reg_GPIO_GIUS(GPIOE) &= 0xFFFF0FFF;	// clear bit 12-bit 15 of GIUS_E
	_reg_GPIO_GPR(GPIOE) &= 0xFFFF0FFF;	// clear bit 12-bit 15 of GPR_E

	//=================================================================

        _reg_GPIO_GIUS(GPIOE) &= ~0x00000d8;      //port E pin 3,4,6,7 for uart2
        _reg_GPIO_GPR(GPIOE) &= ~0x00000d8;       //port E pin 3,4,6,7 for primary function
	if (_reg_SYS_FMCR & 0xC0000000)
	     {
		// connect CLKO to CLK48M
		temp = _reg_CRM_CSCR;
		temp &= ~0xe0000000;
		//fma temp |= 0x40000000;
		_reg_CRM_CSCR = temp;  //gary add it according to Frank Ma's advice
                
		//gary add: change for NFC clock(/12) NAND flash programming
		temp = _reg_CRM_PCDR0;
		temp &= ~0xF000;
		temp |= 0xB000;

		_reg_CRM_PCDR0 = temp;	
		}
		else
		{
		//PLL bypass mode (SPLL = 48MHz)
		//configure the Clock - usbdiv=0 (/1), clkdiv=0
		temp = _reg_CRM_CSCR;
		temp &= ~0x1C000000;
		_reg_CRM_CSCR = temp;   //gary add it according to Frank Ma's advice
		}

}   
#endif
#if defined(__ASSEMBLER__) 
/*
 * Platform setup macro
 */
#define PLATFORM_SETUP1 _platform_setup1
//#define SOURCE 0xDF0031f8
//#define TARGET  0xc00031f8

//definitions from redboot\cvs\src\packages\hal\arm\mx21\evb\current\include\hal_platform_setup.h
// This macro represents the initial startup code for the platform
        .macro  _platform_setup1
MX21_SETUP_START:
   // size is stored in location 0x0C0000FC
	.global	_start
_start:	
	.word   0xE59FF000	
	.word   0	
	.word   ( _start2 - 4 )	
	.word	0
	.word	( _start2 - 4 )
_loop1:	b	_loop1	
	nop	
	nop	
	nop	
	nop	
	nop	
	nop	
	nop
	
_start2:     
	ldr r1,=0x10000000     
	ldr r3,=0x00040304      
	str r3,[r1]                  
	ldr r1,=0x10020000     
	ldr r3,=0x00000000     
	str r3,[r1]       
	ldr r1,=0x10000004       
	ldr r3,=0xFFFBFCFB        
	str r3,[r1]        
	ldr r1,=0x10020004      
	ldr r3,=0xFFFFFFFF       
	str r3,[r1]  

//# Explicitly set MPLL 266MHz
//comment setmem 0x10027004 0x007b1C73 32     
	ldr r1,=0x10027004    
	ldr r3,=0x007b1C73        
	str r3,[r1]        
	
//comment comment # PLL 66MHz
//comment setmem 0x10027000 0x1700C207 32  

	ldr r1,=0x10027000   
	ldr r3,=0x77000207   
	str r3,[r1]     

//comment comment # PLL 88.67MHz
//setmem 0x10027000 0x17000a07 32
	ldr r1,=0x10027000

//modified for NANDFlash to use 88.67MHz//    
	ldr r3,=0x17000a07      
	ldr r3,=0x17000a07       
	str r3,[r1]     

//comment # PLL 133MHz
//comment setmem 0x10027000 0x17000607 32

	//comment # CS0 Initialization (Async Mode)  
	//comment # 32-bit, ?? wait states       
	//setmem 0xDF001000 0x00003E00 32
	//setmem 0xDF001004 0x00000E01 32   
	ldr r1,=0xDF001000     
	ldr r3,=0x00003E00       
	str r3,[r1]   
	ldr r1,=0xDF001004   
	ldr r3,=0x00000E01    
	str r3,[r1]

//comment # CS3 Initialization (Async Mode)
//comment # 32-bit, ?? wait states
//setmem 0xDF001018 0x00003E00 32
//setmem 0xDF00101C 0x11110601 32     
	ldr r1,=0xDF001018
	ldr r3,=0x00003E00   
	str r3,[r1]         
	ldr r1,=0xDF00101c    
	ldr r3,=0x11110601     
	str r3,[r1]

//comment # FMCR Register
//comment # Select CS3 and CSD0
//setmem 0x10027814 0xFFFFFFC9 32         
	ldr r1,=0x10027814
	ldr r3,=0xFFFFFFC9 
	str r3,[r1] 

//comment Set Precharge Command
//setmem 0xDF000000 0x92120300 32   
	ldr r1,=0xDF000000        
	ldr r3,=0x92120300     
	str r3,[r1]            

//comment Issue Precharge all Command
//memory 0xC0200000 +1 32             
	LDR  r3, =0xC0200000     
	LDR  r2, [r3] 

//comment Set AutoRefresh Command
//setmem 0xDF000000 0xA2120300 32   

	LDR  r3, =0xA2120300     
	STR  r3, [r1]      
	
//  Issue AutoRefresh Command        
	LDR  r3, =0xC0000000   
	LDR  r2, [r3]      
	LDR  r2, [r3]      
	LDR  r2, [r3]     
	LDR  r2, [r3]     
	LDR  r2, [r3]      
	LDR  r2, [r3]      
	LDR  r2, [r3]     
	LDR  r2, [r3] 

//comment Set Mode Register
//setmem 0xDF000000 0xB2120300 32

	LDR  r3, =0xB2120300     
	STR  r3, [r1]  
//comment Issue Mode Register Command
//comment Burst Length = 8
//memory 0xC0119800 +1 32       
	LDR  r3, =0xC0119800
	
//; Mode Register Value      
 	LDR  r2, [r3] 

//comment Set to Normal Mode
//comment # From the spec of the SDRAM K4S56163LC-RG75000,
//comment # 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b 
//comment # 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b
//comment # 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b 
//comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
//setmem 0xDF000000 0x8212F339 32    
	LDR  r3, =0x8212F339         
	STR  r3, [r1] 
	
//comment increase the driving strength for i.MX21 after 0440		
	ldr	r3,=0x10027824		
	ldr r0,=0x12491249	
	ldr r2,=0x9
	
_DrivingLoop:		
	str	r0,[r3]		
	add	r3,r3,#4		
	sub	r2,r2,#1	
	teq	r2,#0		
	beq	_EndDriving		
	b	_DrivingLoop		
_EndDriving:	
//;***************************************
//;*  End of SDRAM and SyncFlash Init    *
//;*************************************** 
// copy code from FLASH to SRAMcopyCodes:     
/*        ldr     r0,=SOURCE 
        ldr     r1,=TARGET    
        sub     r3,r0,#4     
        ldr     r2,[r3]
   _CopyLoop:      
   	ldr     r3,[r0]     
	str     r3,[r1]     
	add     r0,r0,#4   
	add     r1,r1,#4   
	sub     r2,r2,#4       
	teq     r2,#0       
	beq     _EndCopy    
	b       _CopyLoop
_EndCopy:      
	ldr     r0,=TARGET      
	mov     pc,r0*/
 .endm
#endif  /* defined(__ASSEMBLER__) */

/*---------------------------------------------------------------------------*/
#endif /* End of MXC_SETUP_MX21_H_ */