mxc_setup_mxc91131.h

i.mx31 3DS平台Nandboot引导程序源码

 *      AP_PAT_REF_DIV = /1 = (0 << 15)         = 0x00000000
 *      CRS = uncorrected PAT_REF = (0 << 16)   = 0x00000000
 *                                              ------------
 *                                                0x00005540
 */
        ldr r1, =0x00005540
        str r1, [r2, #CRM_AP_ASCSR]

/*
 * Configure ADPLL control register (DP_CTL):
 *      BRMO = second order = (1 << 1)          = 0x00000002
 *      PLM = freq only lock = (0 << 2)         = 0x00000000
 *      RCP = pos edge = (0 << 3)               = 0x00000000
 *      RST = no restart = (0 << 4)             = 0x00000000
 *      UPEN = PLL enable = (0 << 5)            = 0x00000020
 *      PRE = no reset = (0 << 6)               = 0x00000000
 *      HFSM = normal mode = (0 << 7)           = 0x00000000
 *      REF_CLK_SEL = ckih_camp_x2 = (2 << 8)   = 0x00000200
 *      REF_CLK_DIV = /1 = (0 << 10)            = 0x00000000
 *                                              ------------
 *                                                0x00000222
 */
        ldr r1, =0x00000222
        str r1, [r0, #DPLL_DP_CTL]

/*
 * Wait for ADPLL to lock
 */
adpll_lock:
        ldr r1, [r0, #DPLL_DP_CTL]
        ands r1, r1, #(1 << 0)
        beq adpll_lock
 
/*
 * Configure AP clock selection register (CRM_AP_ACSR):
 *      ACS = PLL_CLK = (1 << 0)                = 0x00000001
 *      WPS = PLL_CLK in wait mode = (0 << 1)   = 0x00000000
 *      PDS = PLL on in stop mode  = (0 << 2)   = 0x00000000
 *      SMD = use sync muxes = (1 << 3)         = 0x00000000
 *      DI = ignore dsm_int = (0 << 7)          = 0x00000000
 *      ADS = non-doubler path = (0 << 8)       = 0x00000000
 *                                              ------------
 *                                                0x00000001
 */
        ldr r1, =0x00000001
        str r1, [r2, #CRM_AP_ACSR]
 
udpll_setup:
/*
 * Configure UDPLL registers
 */
        ldr r0, =UDPLL_BASE_ADDR
    
/*
 * Configure UDPLL operation register (DP_OP, DP_HFS_OP):
 */
        ldr r1, =UDPLL_OP
        str r1, [r0, #DPLL_DP_OP]
        str r1, [r0, #DPLL_DP_HFS_OP]
    
/*
 * Configure UDPLL operation register (DP_MFN, DP_HFS_MFN):
 */
        ldr r1, =UDPLL_MFN
        str r1, [r0, #DPLL_DP_MFN]
        str r1, [r0, #DPLL_DP_HFS_MFN]
    
/*
 * Configure UDPLL operation register (DP_MFD, DP_HFS_MFN):
 */
        ldr r1, =UDPLL_MFD
        str r1, [r0, #DPLL_DP_MFD]
        str r1, [r0, #DPLL_DP_HFS_MFD]

/*
 * Configure UDPLL control register (DP_CTL):
 *      BRMO = second order = (1 << 1)          = 0x00000002
 *      PLM = freq only lock = (0 << 2)         = 0x00000000
 *      RCP = pos edge = (0 << 3)               = 0x00000000
 *      RST = no restart = (0 << 4)             = 0x00000000
 *      UPEN = PLL enable = (0 << 5)            = 0x00000020
 *      PRE = no reset = (0 << 6)               = 0x00000000
 *      HFSM = normal mode = (0 << 7)           = 0x00000000
 *      REF_CLK_SEL = ckih_camp = (0 << 8)      = 0x00000000
 *      REF_CLK_DIV = /1 = (0 << 10)            = 0x00000000
 *                                              ------------
 *                                                0x00000022
 */
        ldr r1, =0x00000022
        str r1, [r0, #DPLL_DP_CTL]

/*
 * Wait for UDPLL to lock
 */
udpll_lock:
        ldr r1, [r0, #DPLL_DP_CTL]
        ands r1, r1, #(1 << 0)
        beq udpll_lock

/*
 * Configure AP accessory clock register (CRM_AP_ACDER1):
 *      SSI1DIV = /12.5 = (0x19 << 0)           = 0x00000019
 *      SSI1EN = off = (0 << 6)                 = 0x00000000
 *      SSI2DIV = /12.5 = (0x19 << 8)           = 0x00001900
 *      SSI2EN = off = (0 << 14)                = 0x00000000
 *      FIRIEN = off = (1 << 22)                = 0x00000000
 *      CSEN = off = (0 << 20)                  = 0x00000000
 *                                              ------------
 *                                                0x00001919
 */
        ldr r1, =(0x00001919 | (FIRI_DIV << 16) | (CS_DIV << 24))
        str r1, [r2, #CRM_AP_ACDER1]

/*
 * Configure AP accessory clock register (CRM_AP_ACDER2):
 *      BAUD_DIV = /1 = (8 << 0)                = 0x00000008
 *      BAUD_ISEL = CKIH_X2 = (1 << 5)          = 0x00000020
 *      USBEN = USB_CLK enabled = (1 << 12)     = 0x00001000
 *      NFCEN = NFC_CLK enabled = (1 << 20)     = 0x00100000
 *                                              ------------
 *                                                0x00101028
 */
        ldr r1, =(0x00101028 | (NFC_DIV << 16) | (USB_DIV << 8))  /* NFC 19Mhz */
        str r1, [r2, #CRM_AP_ACDER2]


/*
 * End of Step 5: Clock setup
 */

/*
 * Step 6: M3IF/WEIM/ESDCTL setup
 */
        
        /* WEIM setup */
        /* CS0 setup */
#ifndef FLASH_BURST_MODE_ENABLE
        /*
         * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
         */
        /* Flash reset command */
        ldr     r0, =CS0_BASE_ADDR
        ldr     r1, =0xF0F0
        strh    r1, [r0]
        /* 1st command */
        ldr     r2, =0xAAA
        add     r2, r2, r0
        ldr     r1, =0xAAAA
        strh    r1, [r2]
        /* 2nd command */
        ldr     r2, =0x554
        add     r2, r2, r0
        ldr     r1, =0x5555
        strh    r1, [r2]
        /* 3rd command */
        ldr     r2, =0xAAA
        add     r2, r2, r0
        ldr     r1, =0xD0D0
        strh    r1, [r2]
        /* Write flash config register */
        ldr     r1, =0x56CA
        strh    r1, [r2]
        /* Flash reset command */
        ldr     r1, =0xF0F0
        strh    r1, [r0]

        ldr r0, =WEIM_BASE_ADDR
        ldr r1, =0x23524E80
        str r1, [r0, #CSCRU]
        ldr r1, =0x10000D03
        str r1, [r0, #CSCRL]
        ldr r1, =0x00720900
        str r1, [r0, #CSCRA]

        /* Async flash mode */
        ldr r0, =WEIM_CTRL_CS0
        ldr r1, =0x11414C80
        str r1, [r0, #CSCRU]
        ldr r1, =0x30000D03
        str r1, [r0, #CSCRL]
        ldr r1, =0x00310800
        str r1, [r0, #CSCRA]
#endif

        /* CPLD on CS4 setup */
        ldr r0, =WEIM_CTRL_CS4

        ldr r1, =0x0000D843
        str r1, [r0, #CSCRU]
        ldr r1, =0x22252521
        str r1, [r0, #CSCRL]
        ldr r1, =0x22220A00
        str r1, [r0, #CSCRA]

        /* If SDRAM has been setup, bypass clock/WEIM setup */
        ldr r3, =ESDCTL_BASE
        ldr r1, [r3]
        ands r1, r1, #0x80000000
        bne HWInitialise_skip_SDRAM_setup

init_sdram:  /* Get here only when not boot out of SDRAM */

        /* Assuming DDR memory first */
        ldr r3, =0x82226080     /* 32 bit memory */
        init_ddr_sdram
        /* Testing if it is truly DDR */
        ldr r1, =SDRAM_COMPARE_CONST1
        ldr r0, =SDRAM_BASE_ADDR
        str r1, [r0]
        ldr r2, =SDRAM_COMPARE_CONST2
        str r2, [r0, #0x4]
        ldr r2, [r0]
        cmp r1, r2
        beq HWInitialise_skip_SDRAM_setup

        ldr r3, =0x82216080     /* 16 bit memory */
        init_ddr_sdram
        /* Testing if it is truly DDR */
        ldr r1, =SDRAM_COMPARE_CONST1
        ldr r0, =SDRAM_BASE_ADDR
        str r1, [r0]
        ldr r2, =SDRAM_COMPARE_CONST2
        str r2, [r0, #0x4]
        ldr r2, [r0]
        cmp r1, r2
        beq HWInitialise_skip_SDRAM_setup

        /* Reach here ONLY when SDR */
        ldr r3, =0x82126180     /* 32 bit memory */
        init_sdr_sdram
        /* Still test to make sure SDR */
        ldr r1, =SDRAM_COMPARE_CONST1
        ldr r0, =SDRAM_BASE_ADDR
        str r1, [r0]
        ldr r2, =SDRAM_COMPARE_CONST2
        str r2, [r0, #0x4]
        ldr r2, [r0]
        cmp r1, r2
        beq HWInitialise_skip_SDRAM_setup

        ldr r3, =0x82116180     /* 16 bit memory */
        init_sdr_sdram
        /* Still test to make sure SDR */
        ldr r1, =SDRAM_COMPARE_CONST1
        ldr r0, =SDRAM_BASE_ADDR
        str r1, [r0]
        ldr r2, =SDRAM_COMPARE_CONST2
        str r2, [r0, #0x4]
        ldr r2, [r0]
        cmp r1, r2
        beq HWInitialise_skip_SDRAM_setup

        /* Reach hear means memory setup problem. Try to 
         * increase the HCLK divider */
        ldr r0, =CRM_AP_BASE_ADDR
        ldr r1, [r0, #CRM_AP_ACDR]
        and r2, r1, #0xF0
        cmp r2, #0xF0
        beq loop_forever
        add r1, r1, #0x10
        str r1, [r0, #CRM_AP_ACDR]
        b init_sdram

loop_forever:
        b loop_forever  /* shouldn't get here */

HWInitialise_skip_SDRAM_setup:


/*
 * End of Step 6: M3IF/WEIM/ESDCTL setup
 */

HWInitialise_skip_SDRAM_copy:

NAND_ClockSetup:
		.endm
	

/*
 * Note:
 *     IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
 */

	// DDR SDRAM setup
    /* r3 = value for ESDCTL0 */
    .macro  init_ddr_sdram
        ldr r0, =ESDCTL_BASE
        ldr r2, =SDRAM_BASE_ADDR
        ldr r1, =0x0075E73A
        str r1, [r0, #0x4]
        ldr r1, =0x2            // reset
        str r1, [r0, #0x10]
        ldr r1, =0x4            // DDR
        str r1, [r0, #0x10]

        // Hold for more than 200ns
        ldr r1, =0x10000
1:
        subs r1, r1, #0x1
        bne 1b

        ldr r1, =0x92100000
        str r1, [r0]
        ldr r1, =0x12344321
        ldr r12, =0x80000F00
        str r1, [r12]
        ldr r1, =0xA2100000
        str r1, [r0]
        ldr r1, =0x12344321
        str r1, [r2]
        str r1, [r2]

        ldr r1, =0xB2100000
        str r1, [r0]

        ldr r1, =0xDA
        strb r1, [r2, #0x33]

        ldr r1, =0xFF
        ldr r12, =0x81000000
        strb r1, [r12]
        str r3, [r0]
        ldr r1, =0xDEADBEEF
        str r1, [r2]
        ldr r1, =0x0000000C
        str r1, [r0, #0x10]
    .endm

// SDR SDRAM setup
    /* r3 = value for ESDCTL0 */
    .macro  init_sdr_sdram
        ldr r0, =ESDCTL_BASE
        ldr r2, =SDRAM_BASE_ADDR
        ldr r1, =0x0075E73A
        str r1, [r0, #0x4]
        ldr r1, =0x2            // reset
        str r1, [r0, #0x10]
        ldr r1, =0x0            // sdr
        str r1, [r0, #0x10]

        // Hold for more than 200ns
        ldr r1, =0x10000
1:
        subs r1, r1, #0x1
        bne 1b

        ldr r1, =0x92126080
        str r1, [r0]
        ldr r1, =0x0
        ldr r12, =0x80000400
        str r1, [r12]
        ldr r1, =0xA2126080
        str r1, [r0]

        ldr r1, =0x0
        str r1, [r2]
        str r1, [r2]

        ldr r1, =0xB2126180
        str r1, [r0]

        ldr r1, =0x0
        strb r1, [r2, #0x37]
        ldr r12, =0x81000000
        str r1, [r12]
        str r3, [r0]
        ldr r1, =0x0
        str r1, [r2]
    .endm


#endif  /* defined(__ASSEMBLER__) */

/*---------------------------------------------------------------------------*/
#endif /* End of MXC_SETUP_MXC91131_H */