mxc_setup_mxc91131.h

i.mx31 3DS平台Nandboot引导程序源码

#define         PLL_DP_HFS_MFN      0x24

#define         L2CC_ENABLED
#define         UART_WIDTH_32         /* internal UART is 32bit access only */



#define         HAL_DELAY_US(n)     hal_delay_us(n)

#define         CKIH_CLK_FREQ       16800000
#define         DIGRF_CLK_FREQ      26000000
#define         PLL_REF_CLK         (CKIH_CLK_FREQ * 2)


//definitions from redboot\cvs\src\packages\hal\arm\mxc91131\evb\current\include\hal_platform_setup.h

#define         FLASH_BURST_MODE_ENABLE 1
#define         SDRAM_COMPARE_CONST1    0x55555555
#define         SDRAM_COMPARE_CONST2    0xAAAAAAAA
//Definitions from redboot\cvs\src\packages\hal\arm\mxc91131\evb\current\include\mxc91131.h
#define         PBC_BASE                    CS4_BASE_ADDR    /* Peripheral Bus Controller */
#define         MXC91131EVB_CS_LAN_BASE         (CS4_BASE_ADDR + 0x00020000 + 0x300)
#define         MXC91131EVB_CS_UART_BASE        (CS4_BASE_ADDR + 0x00010000)

#define         REDBOOT_IMAGE_SIZE          0x40000

#define         SDRAM_WORKAROUND_FULL_PAGE
#define         SDRAM_X32

#define         APCLK_399_133_66            /* AP_CLK: 399 MHz, AP_AHB_CLK = 133 MHz, AP_IP_CLK = 66.5 MHz */
#define         USB_PLL_CLK_96              /* USB_PLL_CLK: 96 MHz */
#define         UART_FIFO_CTRL          0xA01
#ifdef          APCLK_532_133_66
#define         ADPLL_PDF   (1)
#define         ADPLL_MFI   (8)
#define         ADPLL_MFN   (-140)
#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     4
#define         IP_DIV      8
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          APCLK_399_133_66
#define         ADPLL_PDF   (1)
#define         ADPLL_MFI   (6)
#define         ADPLL_MFN   (-105)
#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     3
#define         IP_DIV      6
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          APCLK_266_133_66
#define         ADPLL_PDF   (2)
#define         ADPLL_MFI   (8)
#define         ADPLL_MFN   (-140)
#define         ADPLL_MFD   (1680 - 1)
#define         ADPLL_OP    ((ADPLL_MFI << 4) | (ADPLL_PDF - 1))
#define         ARM_DIV     8   /* 8 => /1 */
#define         AHB_DIV     2
#define         IP_DIV      4
#define         CRM_AP_DIV  ((ARM_DIV << 8) | (AHB_DIV << 4) | (IP_DIV))
#define         NFC_DIV     6   /* 6 => /7 */
#endif

#ifdef          USB_PLL_CLK_96
#define         UDPLL_PDF   (1)
#define         UDPLL_MFI   (5)
#define         UDPLL_MFN   (7142)
#define         UDPLL_MFD   (10000 - 1)
#define         UDPLL_OP    ((UDPLL_MFI << 4) | (UDPLL_PDF - 1))
#define         USB_DIV     0       /* 0 => /2 */
#define         FIRI_DIV    1       /* 1 => /2 */
#define         CS_DIV      0x19    /* 0x19 => /12.5 */
#endif
#define         TIMEOUT                 4000

/* MXC91131 EVB SDRAM is from 0x80000000, 64M */
#define         SDRAM_BASE_ADDR         CSD0_BASE_ADDR

#ifdef  SDRAM_X32
#define          SDRAM_SIZE              0x04000000
#else
#define          SDRAM_SIZE              0x02000000
#endif //SDRAM_X32

#define SETUP_IOMUX()  { }                                       
#if defined(__ASSEMBLER__) 
/*
 * Platform setup macro
 */
#define PLATFORM_SETUP1 _platform_setup1


//definitions from redboot\cvs\src\packages\hal\arm\mxc91131\evb\current\include\hal_platform_setup.h
// This macro represents the initial startup code for the platform
        .macro  _platform_setup1
MXC91131_SETUP_START:
        /*
         * - set correct memory timings & bus widths
         * - configure chip select lines
         * - init anything that could be undefined after reset
         */
/*
 * Step 1: ARM1136 init
 *       - invalidate I/D cache/TLB and drain write buffer;
 *       - invalidate L2 cache
 *       - unaligned access
 *       - branch predictions
 */
        mrc 15, 0, r0, c1, c0, 0        /* r0 = system control reg */
        bic r0, r0, #(1 << 12)          /* disable ICache */
        bic r0, r0, #(1 << 2)           /* disable DCache */
        bic r0, r0, #(1 << 0)           /* disable MMU */
        mcr 15, 0, r0, c1, c0, 0        /* update system control reg */
#ifdef TURN_OFF_IMPRECISE_ABORT
        mrs    r0, cpsr
        bic    r0, r0, #0x100
        msr    cpsr, r0
#endif

        mov r0, #0
        mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
        mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
        mcr 15, 0, r0, c7, c10, 4        /* Drain the write buffer */

        /* Also setup the Peripheral Port Remap register inside the core */
        ldr r0, =0x40000015        /* start from AIPS 2GB region */
        mcr p15, 0, r0, c15, c2, 4
        
        /*** L2 Cache setup/invalidation/disable ***/
        /* Disable L2 cache first */
        ldr r0, =L2CC_BASE_ADDR
        ldr r2, [r0, #L2_CACHE_CTL_REG]
        bic r2, r2, #0x1
        str r2, [r0, #L2_CACHE_CTL_REG]
        /*
         * Configure L2 Cache:
         * - 128k size(16k way)
         * - 8-way associativity
         * - 0 ws TAG/VALID/DIRTY
         * - 4 ws DATA R/W
         */
        ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
        and r1, r1, #0xFE000000
        ldr r2, =0x00030024
        orr r1, r1, r2
        str r1, [r0, #L2_CACHE_AUX_CTL_REG]

        /* Invalidate L2 */
        ldr r1, =0x000000FF
        str r1, [r0, #L2_CACHE_INV_WAY_REG]
L2_loop:
        /* Poll Invalidate By Way register */
        ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
        cmp r2, #0
        bne L2_loop

        /*** End of L2 operations ***/

/*
 * End of Step 1: ARM1136 init
 */

/*
 * Step 2: setup SPBA to allow all 3 masters to have access to these shared peripherals
 */
        
/*
 * End of Step 2: SPBA setup
 */

/*
 * Step 3: AIPI setup
 *        Only setup MPROTx registers. The PACR default values are good.
 */
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
         * not forced to user-mode.
         */
        ldr r0, =AIPS1_CTRL_BASE_ADDR
        ldr r1, =0x77777777
        str r1, [r0, #0x00]
        str r1, [r0, #0x04]
        ldr r0, =AIPS2_CTRL_BASE_ADDR
        str r1, [r0, #0x00]
        str r1, [r0, #0x04]

        /*
         * Clear the on and off peripheral modules Supervisor Protect bit
         * for SDMA to access them. Did not change the AIPS control registers
         * (offset 0x20) access type
         */
        ldr r0, =AIPS1_CTRL_BASE_ADDR
        ldr r1, =0x0
        str r1, [r0, #0x40]
        str r1, [r0, #0x44]
        str r1, [r0, #0x48]
        str r1, [r0, #0x4C]
        ldr r1, [r0, #0x50]
        and r1, r1, #0x00FFFFFF
        str r1, [r0, #0x50]

        ldr r0, =AIPS2_CTRL_BASE_ADDR
        ldr r1, =0x0
        str r1, [r0, #0x40]
        str r1, [r0, #0x44]
        str r1, [r0, #0x48]
        str r1, [r0, #0x4C]
        ldr r1, [r0, #0x50]
        and r1, r1, #0x00FFFFFF
        str r1, [r0, #0x50]
/*
 * End of Step 3: AIPI setup
 */

/*
 * Step 4: MAX (Multi-Layer AHB Crossbar Switch) setup
 */
        ldr r0, =MAX_BASE_ADDR
        /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
        ldr r1, =0x00302154
        str r1, [r0, #0x000]        /* for S0 */
        str r1, [r0, #0x100]        /* for S1 */
        str r1, [r0, #0x200]        /* for S2 */
        str r1, [r0, #0x300]        /* for S3 */
        str r1, [r0, #0x400]        /* for S4 */
        /* SGPCR - always park on last master */
        ldr r1, =0x10
        str r1, [r0, #0x010]        /* for S0 */
        str r1, [r0, #0x110]        /* for S1 */
        str r1, [r0, #0x210]        /* for S2 */
        str r1, [r0, #0x310]        /* for S3 */
        str r1, [r0, #0x410]        /* for S4 */
        /* MGPCR - restore default values */
        ldr r1, =0x0
        str r1, [r0, #0x800]        /* for M0 */
        str r1, [r0, #0x900]        /* for M1 */
        str r1, [r0, #0xA00]        /* for M2 */
        str r1, [r0, #0xB00]        /* for M3 */
        str r1, [r0, #0xC00]        /* for M4 */
        str r1, [r0, #0xD00]        /* for M5 */
/*
 * End of Step 4: MAX setup
 */

/*
 * Step 5: Clock setup
 * 
 */
        ldr r0, =ADPLL_BASE_ADDR
        ldr r2, =CRM_AP_BASE_ADDR
        ldr r3, =CRM_COM_BASE_ADDR

/*
 * If PLL has already been configured via RVD script, skip
 * ADPLL clock setup.  Running ADPLL setup again can
 * cause strange behaviors and loss of communication with
 * RVD.
 */
        ldr r1, [r2, #CRM_AP_ACSR]
        ands r1, r1, #(1 << 0)
        bne udpll_setup
    
/*
 * Configure ADPLL operation register (DP_OP, DP_HFS_OP):
 */
        ldr r1, =ADPLL_OP
        str r1, [r0, #DPLL_DP_OP]
        str r1, [r0, #DPLL_DP_HFS_OP]
    
/*
 * Configure ADPLL operation register (DP_MFN, DP_HFS_MFN):
 */
        ldr r1, =ADPLL_MFN
        str r1, [r0, #DPLL_DP_MFN]
        str r1, [r0, #DPLL_DP_HFS_MFN]
    
/*
 * Configure ADPLL operation register (DP_MFD, DP_HFS_MFN):
 */
        ldr r1, =ADPLL_MFD
        str r1, [r0, #DPLL_DP_MFD]
        str r1, [r0, #DPLL_DP_HFS_MFD]

/* 
 * Configure CRM_AP divider register (CRM_AP_ACDR):
 */
        ldr r1, =CRM_AP_DIV
        str r1, [r2, #CRM_AP_ACDR]

    
/* 
 * Configure CRM_COM system control register (CRM_COM_CSCR):
 *      PDN_CLKMON_CKIH = CLKMON on = (0 << 0)  = 0x00000000
 *      NOCK_CKIH = READ-ONLY = (0 << 1)        = 0x00000000
 *      PDN_CLKMON_DIGRF = CLKMON off = (1 << 2)= 0x00000004
 *      NOCK_DIGRF = READ-ONLY = (0 << 3)       = 0x00000000
 *      BY_AMP_CKIH = CAMP used = (0 << 4)      = 0x00000000
 *      PDN_AMP_CKIH = CAMP on = (0 << 5)       = 0x00000000
 *      REG_MOD = one regulator = (0 << 6)      = 0x00000000
 *      DIGRF_CLK_EN = DIGRF enabled = (1 << 7) = 0x00000080
 *      Reserved = (3 << 8)                     = 0x00000300
 *      CNTL = 1.4 V (5 << 11)                  = 0x00002800
 *      MUX_SEL = no test signals = (0 << 14)   = 0x00000000
 *      BP_PDSM_EN = no pseudo DSM = (1 << 16)  = 0x00000000
 *      CKO_SEL = AP CKO = (1 << 17)            = 0x00020000
 *      CKOH_SEL = AP CKOH = (1 << 18)          = 0x00040000
 *      NF_WIDTH = 8-bit = (0 << 19)            = 0x00000000
 *      NF_PG_SIZ = 512 bytes (0 << 20)         = 0x00000000
 *      BY_AMP_DIGRF = CAMP used = (0 << 21)    = 0x00000000
 *      PDN_AMP_DIGRF = CAMP off = (1 << 22)    = 0x00400000
 *      VREG_CTRL = VREG disabled = (1 << 23)   = 0x00800000
 *      CKIH_DBLR_OFF = doubler on = (0 << 24)  = 0x00000000
 *      DIGRF_DBLR_OFF = doubler off = (1 << 25)= 0x02000000
 *      PDD0 = CRM disables ADPLL = (0 << 26)   = 0x00000000
 *      PDD1 = CRM disables BDPLL = (0 << 27)   = 0x00000000
 *      PDD2 = CRM disables UDPLL = (0 << 28)   = 0x00000000
 *      Reserved = (0 << 29)                    = 0x00000000
 *      MRCG_PWR_GT = not gated = (0 << 30)     = 0x00000000
 *      BP_PAT_REF_EN = pat_ref on = (1 << 31)  = 0x80000000 
 *                                              ------------
 *                                                0x82C62B84
 */
        ldr r1, =0x82C62B84
        str r1, [r3, #CRM_COM_CSCR]

/*
 * Wait for CKIH doubler to lock
 */
ckih_x2_lock:
        ldr r1, [r3, #CRM_COM_CCCR]
        ands r1, r1, #(1 << 14)
        beq ckih_x2_lock
 
/*
 * Configure AP clock observation (CRM_AP_ACR):
 *      CKOS = AP_PAT_REF_CLK = (2 << 4)        = 0x00000020
 *      CKOD = CKO enabled = (0 << 7)           = 0x00000000
 *      CKOHDIV = /4 = (2 << 8)                 = 0x00000200
 *      CKOHS = AP_CLK = (1 << 12)              = 0x00001000
 *      CKOHD = CKOH enabled = (0 << 15)        = 0x00000000
 *                                              ------------
 *                                                0x00001220
 */
        ldr r1, =0x00001220
        str r1, [r2, #CRM_AP_ACR]

/* 
 * Configure CRM_AP DFS control register (CRM_AP_ADCR):
 *      DIV_BYP = DFS divider used = (0 << 1)   = 0x00000000
 *      VSTAT = READ-ONLY = (0 << 3)            = 0x00000000
 *      TSTAT = READ-ONLY = (0 << 4)            = 0x00000000
 *      DFS_DIV_EN = non-integer DFS = (0 << 5) = 0x00000000
 *      CLK_ON = PAT_REF during DFS = (1 << 6)  = 0x00000040
 *      ALT_PLL = no DVS ALT PLL = (0 << 7)     = 0x00000000
 *      LFDF = /2 = (1 << 8)                    = 0x00000100
 *      AP_DELAY = 976 us = (32 << 16)          = 0x00200000
 *                                              ------------
 *                                                0x00200140
 */
        ldr r1, =0x00200140
        str r1, [r2, #CRM_AP_ADCR]

/*
 * Configure CRM_AP source clock selection register (CRM_AP_ASCSR):
 *      AP_ISEL = CKIH = (0 << 0)               = 0x00000000
 *      APSEL = ADPLL = (0 << 3)                = 0x00000000
 *      SSISEL = UDPLL  = (2 << 5)              = 0x00000040
 *      SS2SEL = UDPLL  = (2 << 7)              = 0x00000100
 *      FIRISEL = UDPLL = (2 << 9)              = 0x00000400
 *      CSSEL = UDPLL = (2 << 11)               = 0x00001000
 *      USBSEL = UDPLL = (2 << 13)              = 0x00004000