mxc_setup_mxc91231.h

i.mx31 3DS平台Nandboot引导程序源码

         * - set correct memory timings & bus widths
         * - configure chip select lines
         * - init anything that could be undefined after reset
         */
        /*
         * Step 1: ARM1136 init 
         *           - invalidate I/D cache/TLB and drain write buffer; 
         *           - invalidate L2 cache
         *           - unaligned access
         *           - branch predictions
         */
        mov r0, #0
        mcr 15, 0, r0, c7, c7, 0        /* invalidate I cache and D cache */
        mcr 15, 0, r0, c8, c7, 0        /* invalidate TLBs */
        mcr 15, 0, r0, c7, c10, 4       /* Drain the write buffer */

        /* Also setup the Peripheral Port Remap register inside the core */
	ldr r0, =0x40000015        /* start from AIPS 2GB region */
        mcr p15, 0, r0, c15, c2, 4
        /*
         * End of Step 1: ARM1136 init
         */

        /* sas: Enable ICache */
        mrc p15, 0, r1, c1, c0, 0
        orr r1, r1, #0x1000  /* ICache enable */
        orr r1, r1, #0x0002  /* enable ICache (also ensures   */
                                /* that MMU and alignment faults */
                                /* are enabled), MMU disable   */
        mcr p15, 0, r1, c1, c0, 0
        orr r1, r1, #0
        orr r1, r1, #0
        orr r1, r1, #0
        orr r1, r1, #0
        orr r1, r1, #0
        /* End Enable ICache */

        /*
 * Step 2: setup SPBA to allow all 3 masters to have access to these shared peripherals
 */
	ldr r0, =SPBA_CTRL_BASE_ADDR
	ldr r1, =0x7            /* allow all 3 masters access */
	str r1, [r0, #0x0C]
	str r1, [r0, #0x1C]
	str r1, [r0, #0x24]
	str r1, [r0, #0x28]
	str r1, [r0, #0x40]
	str r1, [r0, #0x44]
	str r1, [r0, #0x48]
	str r1, [r0, #0x4C]
	str r1, [r0, #0x50]
	str r1, [r0, #0x54]
	str r1, [r0, #0x58]
	str r1, [r0, #0x5C]
/*
 * End of Step 2: SPBA setup
 */

/*
 * Step 3: AIPI setup 
         * Only setup MPROTx registers. The PACR default values are good.
         */
        /* 
         * Set all MPROTx to be non-bufferable, trusted for R/W, 
         * not forced to user-mode.
         */
        ldr r0, =AIPS1_CTRL_BASE_ADDR
        ldr r1, =0x77777777
        str        r1, [r0, #0x00]                
        str        r1, [r0, #0x04]
        ldr r0, =AIPS2_CTRL_BASE_ADDR
        str        r1, [r0, #0x00]
        str        r1, [r0, #0x04]
        /*
 		 * End of Step 3: AIPI setup
         */

        /* 
         * Step 4: MAX (Multi-Layer AHB Crossbar Switch) setup
         */
        ldr r0, =MAX_BASE_ADDR
        /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
        ldr r1, =0x00302154                
        str        r1, [r0, #0x000]        /* for S0 */
        str        r1, [r0, #0x100]        /* for S1 */
        str        r1, [r0, #0x200]        /* for S2 */
        str        r1, [r0, #0x300]        /* for S3 */
        str        r1, [r0, #0x400]        /* for S4 */
        /* SGPCR - always park on last master */
        ldr r1, =0x10                        
        str        r1, [r0, #0x010]        /* for S0 */
        str        r1, [r0, #0x110]        /* for S1 */
        str        r1, [r0, #0x210]        /* for S2 */
        str        r1, [r0, #0x310]        /* for S3 */
        str        r1, [r0, #0x410]        /* for S4 */
        /* MGPCR - restore default values */
        ldr r1, =0x0
        str        r1, [r0, #0x800]        /* for M0 */
        str        r1, [r0, #0x900]        /* for M1 */
        str        r1, [r0, #0xA00]        /* for M2 */
        str        r1, [r0, #0xB00]        /* for M3 */
        str        r1, [r0, #0xC00]        /* for M4 */
	    str	       r1, [r0, #0xD00]	       /* for M5 */ //Virtio failed to boot when this is enabled
        /*
         * End of Step 4: MAX setup
         */

        /*
         * Step 5: Clock setup
         * After this step, AP domain is running out of PLL0 with:
           
           Module       Freq (MHz) Note
           =========================================================================
           ARM core     399.1  ap_clk
           AHB          133    known as "hclk" for ap_hclk and xxx_ahb_clk's
           IP           66.5   ap_pclk and ap_com_pclk
           UART1/2 baud 26     ap_perclk
           UART3 baud   26     ap_uart3_perclk
           EMI          133    =hclk

         * All other clocks can be figured out based on this. 
         */

        /*
         * Step 5.1: Check if 26MHz clock is present or not.
	     * For CRM_COM module, the only register we care during bootstrap is the CSCR.
	     * We check this register to see if 26MHz is present or not. All the other 
	     * registers are left untouched.
         */
        ldr r0, =CRM_COM_BASE_ADDR
        ldr r1, [r0, #CRM_COM_CSCR]
        ands r1, r1, #0x2       /* test if NOCK_CKIH bit is set or not */
1:        
	    bne 1b					/* stay here forever if 26MHz clock is not present */
        /* Now 26MHz clock is available */
                
                
        /*
	     * Step5.2: Setup PLL0 - ADPLL for AP domain. TODO: correct the comments
	     * Note: 1. The default setting for PLL0 is 200MHz. The following code is 
	     *          to get 399.1MHz for PLL0. As by default HFS mode is selected, 
	     *          we set both HFS & normal mode to the same value.
	     *		    As the HFS mode is used we have to configure DFS Divider disabled 
	     *          to get 399,1MHz on the core. If not it will be 399.1/2 (which causes
	     *          problem to have AHB clock at 133MHz). To disbale the divider, 
	     *          we have to set Bit1 in ADCR register (DIV_BYP bit).
	     *       2. PLL1 and PLL2 are disabled. Setup PLL2 at 48MHz.
	     *       3. Cannot reset the pll because the core will crash.
	     *       4. We prefer to have auto-resart disabled and do the resart manually.
         */
	 
        ldr r0, =PLL0_BASE_ADDR

	ldr r1, =0x22
	str r1, [r0, #PLL_DP_CTL]     /* Set DPLL ON (set UPEN bit); BRMO=1 */
	ldr r1, =0x0
	str r1, [r0, #PLL_DP_CONFIG]  /* Disable auto-restart AREN bit */
        
        /* 
         * Set PLL0 to be 399.1MHz.
         * MFI=7, PDF=0, MFD=39, MFN=27 -> 
         * PLL0=2*26MHzInput*(7+27/(39+1))/(0+1)=399.1 MHz
         */
        ldr r1, =0x70                          
        str r1, [r0, #PLL_DP_OP]
        ldr r1, =39
        str r1, [r0, #PLL_DP_MFD]
     	ldr r1, =27
        str r1, [r0, #PLL_DP_MFN]
                
	ldr r1, =0x70			  
	str r1, [r0, #PLL_DP_HFS_OP]
	ldr r1, =39
	str r1, [r0, #PLL_DP_HFS_MFD]
	ldr r1, =27
	str r1, [r0, #PLL_DP_HFS_MFN]
		
        /* Now restart DPLL */
		ldr r1, =0x32
    	str r1, [r0, #PLL_DP_CTL]
wait_pll0_lock: 
	ldr r1, [r0, #PLL_DP_CTL]
	ands r1, r1, #0x1
	beq wait_pll0_lock

	/* End of PLL0 setup with PLL0 being locked at 399,1MHz */

	/*
 	 * Set PLL2 to 48MHz
 	 */
	ldr r0, =PLL2_BASE_ADDR

        ldr r1, =0x22
	str r1, [r0, #PLL_DP_CTL]     /* Set DPLL ON (set UPEN bit); BRMO=1 */
	ldr r1, =0x0
	str r1, [r0, #PLL_DP_CONFIG]  /* Disable auto-restart AREN bit */

	/* 
	 * Set PLL2 to be 48MHz.
 	 * MFI=12, PDF=12, MFD=0, MFN=0 -> 
 	 * PLL0=2*26MHzInput*(12+0/(0+1))/(12+1)=48 MHz
	 */
	ldr r1, =0xCC		  
	str r1, [r0, #PLL_DP_OP]
	ldr r1, =0
	str r1, [r0, #PLL_DP_MFD]
	ldr r1, =0
	str r1, [r0, #PLL_DP_MFN]

	ldr r1, =0xCC			  
	str r1, [r0, #PLL_DP_HFS_OP]
	ldr r1, =0
	str r1, [r0, #PLL_DP_HFS_MFD]
	ldr r1, =0
	str r1, [r0, #PLL_DP_HFS_MFN]
	
	/* Now restart DPLL */
	ldr r1, =0x32
        str r1, [r0, #PLL_DP_CTL]

wait_pll2_lock: 
        ldr r1, [r0, #PLL_DP_CTL]
        ands r1, r1, #0x1
	beq wait_pll2_lock

	/* End of PLL2 setup with PLL2 being locked at 48MHz */

        /*
         * Step5.3: switching to DPLL for AP domain and restore default register
         * values.
         */
        ldr r0, =CRM_AP_BASE_ADDR
	
        /*Dividers setup */
	//	ldr r1, =0x0836
        ldr r1, =0x0866
	str	r1, [r0, #CRM_AP_ACDR]     	/* ARM core=399.1MHz, AHB=133MHz, IP=66.5MHz */
        ldr r1, =0x0000D540
        str r1, [r0, #CRM_AP_ASCSR] /* restore default value */
        ldr r1, =0x1
        str r1, [r0, #CRM_AP_ACSR]  /* select DPLL for AP domain at new freq */
        ldr r1, =0x05071919
        str r1, [r0, #CRM_AP_ACDER1]    /* restore default */
	//ldr r1, =0x00101808
	//str	r1, [r0, #CRM_AP_ACDER2]	/* set ap_perclk = 26MHz */
	ldr r1, =0x00131809
	str	r1, [r0, #CRM_AP_ACDER2] /* sas: set nfc_div for ~19.4 MHz */

        ldr r1, =0x00244924
        str r1, [r0, #CRM_AP_ACGCR]     /* restore default */
	ldr r1, =0x124
        str r1, [r0, #CRM_AP_ACCGCR]    /* restore default */
        ldr r1, =0x01110101
        str r1, [r0, #CRM_AP_APRA]  /* restore default to enable UART1/2/3 */
	/* Set the DIV_BYP bit */
	ldr r1, =0x00200168
	str	r1, [r0, #CRM_AP_ADCR]		/* set DFS Divider to Not used */
	/* Setup RVAL/WVAL for internal memories */
	ldr r1, =0x00060105
	str	r1, [r0, #CRM_AP_AGPR]

        /*
         * End of Step 5: Clock setup
         */

        /* Drive strength setup for Pass 2.0 */
        ldr r0, =SYSTEM_SREV_REG
        ldr r1, [r0, #0x0]
        cmp r3, #0x0
        beq init_drive_strength_bypass
        /* Required for MXC91231 PASS 2 ONLY for 133MHz SDR */
        ldr r0, =(IOMUX_COM_BASE_ADDR + 0x200)
        ldr r1, =0x0082
        strh r1, [r0, #0x0]
        ldr r1, =0x0002
        strh r1, [r0, #0x2]
        ldr r1, =0x0108
        strh r1, [r0, #0x4]
        ldr r1, =0x0103
        strh r1, [r0, #0x8]
        ldr r1, =0x01C3
        strh r1, [r0, #0xA]
        ldr r1, =0x0183
        strh r1, [r0, #0xC]
init_drive_strength_bypass:

        /*
         * Step 6: M3IF/WEIM/ESDCTL setup
         */
	/* M3IF setup */	
	/* CS0 setup */
        ldr r0, =WEIM_BASE_ADDR
        ldr r1, =0x0000D346
        str r1, [r0, #CSCRU]
        ldr r1, =0x444A4D21
        str r1, [r0, #CSCRL]
        ldr r1, =0x44443302
        str r1, [r0, #CSCRA]
        
        /* CS4 setup */
        ldr r0, =(WEIM_BASE_ADDR + 0x40)
        ldr r1, =0x0000DCF6
        str r1, [r0, #CSCRU]
        ldr r1, =0x444A4541
        str r1, [r0, #CSCRL]
        ldr r1, =0x44443302
        str r1, [r0, #CSCRA]
        
        /* Do SDRAM at CSD1 setup only when not executed from SDRAM */
        ldr r0, =SDRAM_BASE_ADDR
        cmp pc, r0
        blt init_sdram
        ldr r0, =(SDRAM_BASE_ADDR + SDRAM_SIZE)
        cmp pc, r0
        blt HWInitialise_skip_SDRAM_setup
init_sdram:
        ldr r0, =ESDCTL_BASE
        ldr r2, =CSD0_BASE_ADDR
        ldr r1, =0x0079E7BA
        str	r1, [r0, #0x4]
        ldr r1, =0x0
        str	r1, [r0, #0x10]
        ldr r1, =0x92116080
        str	r1, [r0]
        ldr r1, =0x0
        strb r1, [r2, #0x400]
        ldr r1, =0xA2116080
        str r1, [r0]
        
        ldr r1, =0x0
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        strb r1, [r2]
        
        ldr r1, =0xB2116080
        str r1, [r0]
        
        ldr r1, =0x0
#ifdef SDRAM_NO_WORKAROUND
	strb r1, [r2, #0x33]
//	strb r1, [r2, #0x01000000]
	ldr r1, =0x82116080
	str r1, [r0]
	ldr r1, =0x0
	strb r1, [r2]
#else
#ifdef SDRAM_WORKAROUND_FULL_PAGE
	strb r1, [r2, #0x37]
//	strb r1, [r2, #0x01000000]
	ldr r1, =0x82116180
	str r1, [r0]
	ldr r1, =0x0
	strb r1, [r2]
#else
#error What is SDRAM workaround???
#endif /* SDRAM_WORKAROUND_FULL_PAGE */
#endif /* SDRAM_NO_WORKAROUND */


HWInitialise_skip_SDRAM_setup:

        /*
         * End of Step 6: M3IF/WEIM/ESDCTL setup
         */

NAND_ClockSetup:

	.endm

#endif  /* defined(__ASSEMBLER__) */

#endif /* MXC_SETUP_MXC91231_H */