mxc_setup_mxc91231.h

i.mx31 3DS平台Nandboot引导程序源码

#ifndef MXC_SETUP_MXC91231_H
#define MXC_SETUP_MXC91231_H

//=============================================================================
//
//          mxc_setup_mxc91231.h
//
//          Platform specific code for MXC91231 platform 
//          This code is derived from eCos files hal_platform_setup.h
//          hal_platform_setup.h
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2002 Gary Thomas
// Copyright 2004 Freescale Semiconductor, Inc. All Rights Reserved.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/* Definitions from redboot mxc91231/var/current/include/hal_mxc91231.h */

#ifdef __ASSEMBLER__

#define REG8_VAL(a)          (a)
#define REG16_VAL(a)         (a)
#define REG32_VAL(a)         (a)

#define REG8_PTR(a)          (a)
#define REG16_PTR(a)         (a)
#define REG32_PTR(a)         (a)

#else /* __ASSEMBLER__ */

#define REG8_VAL(a)          ((unsigned char)(a))
#define REG16_VAL(a)         ((unsigned short)(a))
#define REG32_VAL(a)         ((unsigned int)(a))

#define REG8_PTR(a)          ((volatile unsigned char *)(a))
#define REG16_PTR(a)         ((volatile unsigned short *)(a))
#define REG32_PTR(a)         ((volatile unsigned long *)(a))

#endif /* __ASSEMBLER__ */

/*
 * MXC91231  Default Memory Layout Definitions
 */

#define         L2CC_BASE_ADDR          0x30000000

/*
 * AIPS 1
 */
#define         AIPS1_BASE_ADDR         0x43F00000
#define         AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
#define         MAX_BASE_ADDR           0x43F04000
#define         EVTMON_BASE_ADDR        0x43F08000
#define         CLKCTL_BASE_ADDR        0x43F0C000  
#define         ETB_SLOT4_BASE_ADDR     0x43F10000
#define         ETB_SLOT5_BASE_ADDR     0x43F14000
#define         ECT_CTIO_BASE_ADDR      0x43F18000
#define         I2C_BASE_ADDR           0x43F80000
#define         MU_BASE_ADDR            0x43F88000
#define         UART1_BASE_ADDR         0x43F90000
#define         UART2_BASE_ADDR         0x43F94000
#define         DSM_BASE_ADDR           0x43F98000
#define         OWIRE_BASE_ADDR         0x43F9C000
#define         SSI1_BASE_ADDR          0x43FA0000
#define         KPP_BASE_ADDR           0x43FA8000
#define         IOMUX_AP_BASE_ADDR      0x43FAC000
#define         CTI_AP_BASE_ADDR        0x43FB8000

/*
 * SPBA global module enabled #0
 */
#define         SPBA_MOD0_BASE_ADDR     0x50000000
#define         MMC_SDHC1_BASE_ADDR     0x50004000
#define         MMC_SDHC2_BASE_ADDR     0x50008000
#define         UART3_BASE_ADDR         0x5000C000
#define         CSPI2_BASE_ADDR         0x50010000
#define         SSI2_BASE_ADDR          0x50014000
#define         SIM_BASE_ADDR           0x50018000
#define         IIM_BASE_ADDR           0x5001C000
#define         CTI_SDMA_BASE_ADDR      0x50020000
#define         USBOTG_CTRL_BASE_ADDR   0x50024000
#define         USBOTG_DATA_BASE_ADDR   0x50028000
#define         CSPI1_BASE_ADDR         0x50030000
#define         SPBA_CTRL_BASE_ADDR     0x5003C000
#define         IOMUX_COM_BASE_ADDR     0x50040000
#define         CRM_COM_BASE_ADDR       0x50044000
#define         CRM_AP_BASE_ADDR        0x50048000
#define         PLL0_BASE_ADDR          0x5004C000
#define         PLL1_BASE_ADDR          0x50050000
#define         PLL2_BASE_ADDR          0x50054000
#define         GPIO4_SH_BASE_ADDR      0x50058000
#define         HAC_BASE_ADDR           0x5005C000

/*
 * SPBA global module enabled #1
 */
#define         SPBA_MOD1_BASE_ADDR     0x52000000
#define         MQSPI_BASE_ADDR         0x52034000
#define         EL1T_BASE_ADDR          0x52038000

/*
 * AIPS 2
 */
#define         AIPS2_BASE_ADDR         0x53F00000
#define         AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
#define         GEMK_BASE_ADDR          0x53F8C000
#define         GPT_AP_BASE_ADDR        0x53F90000
#define         EPIT_AP_BASE_ADDR       0x53F94000
#define         SCC_AP_BASE_ADDR        0x53FAC000
#define         RNGA_BASE_ADDR          0x53FB0000
#define         IPU_CTRL_BASE_ADDR      0x53FC0000
#define         AUDMUX_BASE             0x53FC4000
#define         EDIO_BASE_ADDR          0x53FC8000
#define         GPIO1_AP_BASE_ADDR      0x53FCC000
#define         GPIO2_AP_BASE_ADDR      0x53FD0000
#define         SDMA_BASE_ADDR          0x53FD4000
#define         RTC_BASE_ADDR           0x53FD8000
#define         WDOG1_BASE_ADDR      0x53FDC000
#define         PWM_BASE_ADDR           0x53FE0000
#define         GPIO3_AP_BASE_ADDR      0x53FE4000
#define         WDOG2_BASE_ADDR      0x53FE8000
#define         RTIC_BASE_ADDR          0x53FEC000

/*
 * ROMPATCH and AVIC
 */
#define         ROMPATCH_BASE_ADDR      0x60000000
#define         AVIC_BASE_ADDR          0x68000000

/*
 * NAND, SDRAM, WEIM, M3IF, EMI controllers
 */
#define         EXT_MEM_CTRL_BASE       0xB8000000
#define         NFC_BASE                EXT_MEM_CTRL_BASE
#define         ESDCTL_BASE             0xB8001000
#define         WEIM_BASE_ADDR          0xB8002000
#define         M3IF_BASE               0xB8003000
#define         EMI_CTL_BASE            0xB8004000

/*
 * Memory regions and CS
 */
#define         IPU_MEM_BASE_ADDR       0x70000000
#define         CSD0_BASE_ADDR          0x80000000
#define         CSD1_BASE_ADDR          0x90000000
#define         CS0_BASE_ADDR           0xA0000000
#define         CS1_BASE_ADDR           0xA8000000
#define         CS2_BASE_ADDR           0xB0000000
#define         CS3_BASE_ADDR           0xB2000000
#define         CS4_BASE_ADDR           0xB4000000
#define         CS5_BASE_ADDR           0xB6000000
#define         MAX_S0_BASE_ADDR        0xC0000000

/*
 * IRQ Controller Register Definitions.
 */
#define         AVIC_NIMASK             REG32_PTR(AVIC_BASE_ADDR + (0x04))
#define         AVIC_INTTYPEH           REG32_PTR(AVIC_BASE_ADDR + (0x18))
#define         AVIC_INTTYPEL           REG32_PTR(AVIC_BASE_ADDR + (0x1C))

/* L210 */
#define         L2CC_BASE_ADDR          0x30000000
#define         L2_CACHE_LINE_SIZE      32
#define         L2_CACHE_CTL_REG        0x100
#define         L2_CACHE_AUX_CTL_REG    0x104
#define         L2_CACHE_SYNC_REG       0x730
#define         L2_CACHE_INV_LINE_REG   0x770
#define         L2_CACHE_INV_WAY_REG    0x77C
#define         L2_CACHE_CLEAN_LINE_REG 0x7B0
#define         L2_CACHE_CLEAN_INV_LINE_REG     0x7F0

/* SPBA */
#define         SPBA_IOMUX              0x40
#define         SPBA_CRM_COM            0x44
#define         SPBA_PLL0               0x4C
#define         SPBA_PLL1               0x50
#define         SPBA_PLL2               0x54
#define         SPBA_CRM_AP             0x58

/* CRM_COM */
#define         CRM_COM_CSCR            0x0C

/* CRM_AP */
#define         CRM_AP_ASCSR            0x00
#define         CRM_AP_ACDR             0x04
#define         CRM_AP_ACSR             0x3C
#define         CRM_AP_ACDER1           0x08
#define         CRM_AP_ACDER2           0x0C
#define         CRM_AP_ACGCR            0x10
#define         CRM_AP_ACCGCR           0x14
#define		CRM_AP_ADCR			    0x40
#define 	CRM_AP_AGPR			    0x58
#define         CRM_AP_APRA             0x5C

/* WEIM - CS0 */
#define 	CSCRU				0x00
#define 	CSCRL				0x04
#define 	CSCRA				0x08

/* DPLL */
#define         PLL_DP_CTL              0x00
#define         PLL_DP_CONFIG           0x04
#define         PLL_DP_OP               0x08
#define         PLL_DP_MFD              0x0C
#define         PLL_DP_MFN              0x10
#define 	PLL_DP_HFS_OP		0x1C
#define 	PLL_DP_HFS_MFD		0x20
#define 	PLL_DP_HFS_MFN		0x24

/* ESDRAM parameters */
/* TODO: update required based on AP's team */
#define 	SDRAM_CSD0			0x80000000
#define 	SDRAM_CSD1			0x90000000
#define         PRE_ALL_CMD      0x001
#define         AUTO_REF_CMD            0x010
#define         SET_MODE_REG_CMD        0x011
#define         MODE_REG_VAL0           0x000
#define         NORMAL_MODE             0x000

/*
 * UART Control Register 0 Bit Fields.
 */
#define         EUartUCR1_ADEN          (1 << 15)  // Auto detect interrupt
#define         EUartUCR1_ADBR          (1 << 14)  // Auto detect baud rate
#define         EUartUCR1_TRDYEN        (1 << 13)  // Transmitter ready interrupt enable
#define         EUartUCR1_IDEN          (1 << 12)  // Idle condition interrupt
#define         EUartUCR1_RRDYEN        (1 << 9)   // Recv ready interrupt enable
#define         EUartUCR1_RDMAEN        (1 << 8)   // Recv ready DMA enable
#define         EUartUCR1_IREN          (1 << 7)   // Infrared interface enable
#define         EUartUCR1_TXMPTYEN 	(1 << 6)	// Transimitter empty interrupt enable
#define         EUartUCR1_RTSDEN        (1 << 5)   // RTS delta interrupt enable
#define         EUartUCR1_SNDBRK        (1 << 4)   // Send break
#define         EUartUCR1_TDMAEN        (1 << 3)   // Transmitter ready DMA enable
#define         EUartUCR1_DOZE          (1 << 1)   // Doze
#define         EUartUCR1_UARTEN        (1 << 0)   // UART enabled
#define         EUartUCR2_ESCI          (1 << 15)  // Escape seq interrupt enable
#define         EUartUCR2_IRTS          (1 << 14)  // Ignore RTS pin
#define         EUartUCR2_CTSC          (1 << 13)  // CTS pin control
#define         EUartUCR2_CTS           (1 << 12)  // Clear to send
#define         EUartUCR2_ESCEN         (1 << 11)  // Escape enable
#define         EUartUCR2_PREN          (1 << 8)   // Parity enable
#define         EUartUCR2_PROE          (1 << 7)   // Parity odd/even
#define         EUartUCR2_STPB          (1 << 6)   // Stop
#define         EUartUCR2_WS            (1 << 5)   // Word size
#define         EUartUCR2_RTSEN         (1 << 4)   // Request to send interrupt enable
#define         EUartUCR2_ATEN          (1 << 3)   // Aging timer enable
#define         EUartUCR2_TXEN          (1 << 2)   // Transmitter enabled
#define         EUartUCR2_RXEN          (1 << 1)   // Receiver enabled
#define         EUartUCR2_SRST_         (1 << 0)   // SW reset
#define         EUartUCR3_PARERREN      (1 << 12)  // Parity enable
#define         EUartUCR3_FRAERREN      (1 << 11)  // Frame error interrupt enable
#define         EUartUCR3_ADNIMP        (1 << 7)   // Autobaud detection not improved
#define         EUartUCR3_RXDSEN        (1 << 6)   // Receive status interrupt enable
#define         EUartUCR3_AIRINTEN      (1 << 5)   // Async IR wake interrupt enable
#define         EUartUCR3_AWAKEN        (1 << 4)   // Async wake interrupt enable
#define         EUartUCR3_RXDMUXSEL     (1 << 2)   // RXD muxed input selected
#define         EUartUCR3_INVT          (1 << 1)   // Inverted Infrared transmission
#define         EUartUCR3_ACIEN         (1 << 0)   // Autobaud counter interrupt enable
#define         EUartUCR4_CTSTL_32      (32 << 10) // CTS trigger level (32 chars)
#define         EUartUCR4_INVR          (1 << 9)   // Inverted infrared reception
#define         EUartUCR4_ENIRI         (1 << 8)   // Serial infrared interrupt enable
#define         EUartUCR4_WKEN          (1 << 7)   // Wake interrupt enable
#define         EUartUCR4_IRSC          (1 << 5)   // IR special case
#define         EUartUCR4_LPBYP         (1 << 4)   // Low power bypass
#define         EUartUCR4_TCEN          (1 << 3)   // Transmit complete interrupt enable
#define         EUartUCR4_BKEN          (1 << 2)   // Break condition interrupt enable
#define         EUartUCR4_OREN          (1 << 1)   // Receiver overrun interrupt enable
#define         EUartUCR4_DREN          (1 << 0)   // Recv data ready interrupt enable
#define         EUartUFCR_RXTL_SHF      0          // Receiver trigger level shift
#define         EUartUFCR_RFDIV_1       (5 << 7)   // Reference freq divider (div 1)
#define         EUartUFCR_RFDIV_2       (4 << 7)   // Reference freq divider (div 2)
#define         EUartUFCR_TXTL_SHF      10         // Transmitter trigger level shift
#define         EUartUSR1_PARITYERR     (1 << 15)  // Parity error interrupt flag
#define         EUartUSR1_RTSS          (1 << 14)  // RTS pin status
#define         EUartUSR1_TRDY 		(1 << 13) 	// Transmitter ready interrupt/dma flag
#define         EUartUSR1_RTSD          (1 << 12)  // RTS delta
#define         EUartUSR1_ESCF          (1 << 11)  // Escape seq interrupt flag
#define         EUartUSR1_FRAMERR       (1 << 10)  // Frame error interrupt flag
#define         EUartUSR1_RRDY          (1 << 9)   // Receiver ready interrupt/dma flag
#define         EUartUSR1_AGTIM         (1 << 8)   // Aging timeout interrupt status
#define         EUartUSR1_RXDS          (1 << 6)   // Receiver idle interrupt flag
#define         EUartUSR1_AIRINT        (1 << 5)   // Async IR wake interrupt flag
#define         EUartUSR1_AWAKE         (1 << 4)   // Aysnc wake interrupt flag
#define         EUartUSR2_ADET          (1 << 15)  // Auto baud rate detect complete
#define         EUartUSR2_TXFE          (1 << 14)  // Transmit buffer FIFO empty
#define         EUartUSR2_IDLE          (1 << 12)  // Idle condition
#define         EUartUSR2_ACST          (1 << 11)  // Autobaud counter stopped
#define         EUartUSR2_IRINT         (1 << 8)   // Serial infrared interrupt flag
#define         EUartUSR2_WAKE          (1 << 7)   // Wake
#define         EUartUSR2_RTSF          (1 << 4)   // RTS edge interrupt flag
#define         EUartUSR2_TXDC          (1 << 3)   // Transmitter complete
#define         EUartUSR2_BRCD          (1 << 2)   // Break condition
#define         EUartUSR2_ORE           (1 << 1)   // Overrun error
#define         EUartUSR2_RDR           (1 << 0)   // Recv data ready
#define         EUartUTS_FRCPERR        (1 << 13)  // Force parity error
#define         EUartUTS_LOOP           (1 << 12)  // Loop tx and rx
#define         EUartUTS_TXEMPTY        (1 << 6)   // TxFIFO empty
#define         EUartUTS_RXEMPTY        (1 << 5)   // RxFIFO empty
#define         EUartUTS_TXFULL         (1 << 4)   // TxFIFO full
#define         EUartUTS_RXFULL         (1 << 3)   // RxFIFO full
#define         EUartUTS_SOFTRST        (1 << 0)   // Software reset

#define         MXC91231_PERCLK1	26000000	/* Peripheral Clock 1 */
#define         DelayTimerPresVal       3
#define         TIMEOUT                 8000

#define         SYSTEM_SREV_REG     (IIM_BASE_ADDR + 0x24)

/* Definitions from redboot mxc91231/evb/current/include/mxc91231.h */
 
#define         PBC_BASE                         CS4_BASE_ADDR    /* Peripheral Bus
                                                                        Controller */
#define         MXC91231EVB_CS_LAN_BASE                   (PBC_BASE + 0x00020000 + 0x300)
#define         MXC91231EVB_CS_UART_BASE          (PBC_BASE + 0x00010000)

#define         REDBOOT_IMAGE_SIZE               0x40000

#define         SDRAM_BASE_ADDR                  CSD0_BASE_ADDR
#define         SDRAM_SIZE                       0x02000000
#define         RAM_BANK0_BASE                   SDRAM_BASE_ADDR
#define         SDRAM_WORKAROUND_FULL_PAGE
#define         UART_FIFO_CTRL                  0xA01
/* Moved from uart.c */
    
#define SETUP_IOMUX()                                         \
{                                                                 \
        volatile unsigned int *pMuxCtl, *pMuxComCtl;                       \
	pMuxCtl = (volatile unsigned int *)(IOMUX_AP_BASE_ADDR);	\
        pMuxComCtl = (volatile unsigned int *)(IOMUX_COM_BASE_ADDR);	\
        pMuxCtl[83] = (pMuxCtl[83] & 0xFF0FFF0F) | 0x00380024;    	\
        pMuxCtl[84] = (pMuxCtl[84] & 0xFFFF0FFF) | 0x00003000;    	\
	pMuxComCtl[1] = (pMuxComCtl[1] & (0x000000FF)) | 0x20202000;	\
        pMuxCtl[12] = 0x10101010;					\
}                                       
                                  


#if defined(__ASSEMBLER__)
/* 
 * Platform setup macro
 */
#define PLATFORM_SETUP1 _platform_setup1

/* Definitions from redboot mxc91231/evb/current/include/hal_platform_setup.h */
// This macro represents the initial startup code for the platform
        .macro  _platform_setup1
MXC91231_SETUP_START:
        /*