📄 mxc_setup_mxc91331.h
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#ifdef ARMHIPG_52_52_52 ldr r1, =0xFF80051C /* ARM=52MHz, HCLK=52MHz, IPG=52MHz */ str r1, [r0, #CLKCTL_PDR0] ldr r1, =MPCTL_PARAM_208 str r1, [r0, #CLKCTL_MPCTL]#endif#if defined(ARMHIPG_399_133_66) || defined(ARMHIPG_399_66_66) ldr r1, =0x0 ldrb r2, [r1, #0x60] /* See if pass 1 silicon */ cmp r2, #0x1 ldr r1, =0xFF800550 /* ARM=399MHz, HCLK=133MHz, IPG=66.5MHz */ ldreq r1, =0xFF800528 /* For pass 1, HCLK=66.5MHz*/ //ldreq r1, =0xFF800328 /* For pass 1, HCLK=66.5MHz sri NFC 16.625Mhz*/ str r1, [r0, #CLKCTL_PDR0] ldr r1, =MPCTL_PARAM_399 str r1, [r0, #CLKCTL_MPCTL]#endif /* Set to default values */ /* Removed 2 fit in 2k ldr r1, =0x2910AC56 str r1, [r0, #CLKCTL_PDR1] ldr r1, =0x00011401 str r1, [r0, #CLKCTL_UPCTL]*//* * End of Step 6: Clock setup */ /* * Step 7: M3IF/WEIM/ESDCTL setup */ /* M3IF setup */ /* Configure M3IF registers */ ldr r1, =M3IF_BASE /* * M3IF Control Register (M3IFCTL) * MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000 * MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000 * MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 * MRRP[6] = IPU on priority list (1 << 6) = 0x00000040 * MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000 * ------------ * 0x00000040 */ ldr r0, =0x00000040 str r0, [r1] /* M3IF control reg */ /* WEIM setup */ /* CS0 setup */#ifndef FLASH_BURST_MODE_ENABLE /* * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz): */ /* Flash reset command */ ldr r0, =CS0_BASE_ADDR ldr r1, =0xF0F0 strh r1, [r0] /* 1st command */ ldr r2, =0xAAA add r2, r2, r0 ldr r1, =0xAAAA strh r1, [r2] /* 2nd command */ ldr r2, =0x554 add r2, r2, r0 ldr r1, =0x5555 strh r1, [r2] /* 3rd command */ ldr r2, =0xAAA add r2, r2, r0 ldr r1, =0xD0D0 strh r1, [r2] /* Write flash config register */ ldr r1, =0x56CA strh r1, [r2] /* Flash reset command */ ldr r1, =0xF0F0 strh r1, [r0] /* WEIM setup */ ldr r0, =WEIM_BASE_ADDR ldr r1, =0x23524E80 str r1, [r0, #CSCRU] ldr r1, =0x10000D03 str r1, [r0, #CSCRL] ldr r1, =0x00720900 str r1, [r0, #CSCRA]#else /* Async flash mode */ ldr r0, =WEIM_CTRL_CS0 ldr r1, =0x11414C80 str r1, [r0, #CSCRU] ldr r1, =0x30000D03 str r1, [r0, #CSCRL] ldr r1, =0x00310800 str r1, [r0, #CSCRA]#endif /* CPLD on CS4 setup */ ldr r0, =WEIM_CTRL_CS4 ldr r1, =0x0000D843 str r1, [r0, #CSCRU] ldr r1, =0x22252521 str r1, [r0, #CSCRL] ldr r1, =0x22220A00 str r1, [r0, #CSCRA]init_sdram: /* Get here only when not boot out of SDRAM */ /* Assuming DDR memory first */ ldr r3, =0x82226080 /* 32 bit memory */ init_ddr_sdram /* Testing if it is truly DDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup ldr r3, =0x82216080 /* 16 bit memory */ init_ddr_sdram /* Testing if it is truly DDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup /* Reach here ONLY when SDR */ ldr r3, =0x82126180 /* 32 bit memory */ init_sdr_sdram /* Still test to make sure SDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup ldr r3, =0x82116180 /* 16 bit memory */ init_sdr_sdram /* Still test to make sure SDR */ ldr r1, =SDRAM_COMPARE_CONST1 ldr r0, =SDRAM_BASE_ADDR str r1, [r0] ldr r2, =SDRAM_COMPARE_CONST2 str r2, [r0, #0x4] ldr r2, [r0] cmp r1, r2 beq HWInitialise_skip_SDRAM_setup /* Reach hear means memory setup problem. Try to * increase the HCLK divider */ ldr r0, =CRM_MCU_BASE_ADDR ldr r1, [r0, #CLKCTL_PDR0] and r2, r1, #0x38 cmp r2, #0x38 beq loop_forever add r1, r1, #0x8 str r1, [r0, #CLKCTL_PDR0] b init_sdramloop_forever: b loop_forever /* shouldn't get here */HWInitialise_skip_SDRAM_setup:/* * End of Step 7: M3IF/WEIM/ESDCTL setup */HWInitialise_skip_SDRAM_copy:#ifdef DSP_RESET_REQUIRED/* * Deal with DSP reset */ /* Set DSP to LE */ ldr r0, =0x5001C808 ldr r1, [r0] cmp r1, #0x0 beq skip_dsp_reset ldr r1, =0x0 str r1, [r0] ldr r0, =0x43F84024 /* Put DSP in reset */ ldr r1, =0x00000010 str r1, [r0] /* Hold for some time */ ldr r2, =0x80000dsp_reset_delay: subs r2, r2, #0x1 bne dsp_reset_delay /* Put DSP out of reset */ ldr r1, =0x0 str r1, [r0]#endif /* DSP_RESET_REQUIRED */skip_dsp_reset:/* End of DSP reset */NAND_ClockSetup: .endm .macro init_ddr_sdram ldr r0, =ESDCTL_BASE ldr r2, =SDRAM_BASE_ADDR ldr r1, =0x0075E73A str r1, [r0, #0x4] ldr r1, =0x2 // reset str r1, [r0, #0x10] ldr r1, =0x4 // DDR str r1, [r0, #0x10] // Hold for more than 200ns ldr r1, =0x100001: subs r1, r1, #0x1 bne 1b ldr r1, =0x92100000 str r1, [r0] ldr r1, =0x12344321 ldr r12, =0x80000F00 str r1, [r12] ldr r1, =0xA2100000 str r1, [r0] ldr r1, =0x12344321 str r1, [r2] str r1, [r2] ldr r1, =0xB2100000 str r1, [r0] ldr r1, =0xDA strb r1, [r2, #0x33] ldr r1, =0xFF ldr r12, =0x81000000 strb r1, [r12] str r3, [r0] ldr r1, =0xDEADBEEF str r1, [r2] ldr r1, =0x0000000C str r1, [r0, #0x10] .endm// SDR SDRAM setup /* r3 = value for ESDCTL0 */ .macro init_sdr_sdram ldr r0, =ESDCTL_BASE ldr r2, =SDRAM_BASE_ADDR ldr r1, =0x0075E73A str r1, [r0, #0x4] ldr r1, =0x2 // reset str r1, [r0, #0x10] ldr r1, =0x0 // sdr str r1, [r0, #0x10] // Hold for more than 200ns ldr r1, =0x100001: subs r1, r1, #0x1 bne 1b ldr r1, =0x92126080 str r1, [r0] ldr r1, =0x0 ldr r12, =0x80000400 str r1, [r12] ldr r1, =0xA2126080 str r1, [r0] ldr r1, =0x0 str r1, [r2] str r1, [r2] ldr r1, =0xB2126080 str r1, [r0] ldr r1, =0x0 strb r1, [r2, #0x37] ldr r12, =0x81000000 str r1, [r12] str r3, [r0] ldr r1, =0x0 str r1, [r2] .endm#endif /* defined(__ASSEMBLER__) */#endif /* MXC_SETUP_MXC91331_H */⌨️ 快捷键说明
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